Abstract: A method of fabricating a static random access memory. A gate oxide layer is formed on a substrate having active regions of an access transistor and a drive transistor. A Polysilicon layer is formed on the gate oxide layer. A germanium implantation is performed on the polysilicon layer of the active region of the drive region to form a polysilicon germanium layer. Thereafter, the polysilicon layer and the polysilicon germanium layer are patterned to form a poly gate and a polysilicon germanium gate on the active regions of the access transistor and the drive transistor. A lightly doped region is formed in the substrate beside the gates. A spacer is then formed on the sidewall of the gates. A heavily doped region is formed in the substrate beside the spacer.

Abstract: A pressure sensing structure for measuring a local pressure on a surface of a wafer and a wafer carrier for communicating with the wafer is disclosed. The pressure sensing structure includes a conductive via extending through the wafer, a pressure transducer electrically connected to a first side of the conductive via, and a connector arranged in electrical contact with a second side of the conductive via. Further, a wafer incorporating multiple such pressure sensing structures is disclosed. In addition, a pressure sensing structure further including integrated circuitry in electrical contact with the pressure transducer and a conductive via is disclosed. The pressure sensing structure is well suited for use in sensing pressure variations throughout the surface of the wafer when a selected wafer layer is undergoing a chemical mechanical polishing operation.

Abstract: A SCSI external cable for interconnecting external peripheral devices to a host computer system or other peripheral devices is provided. The SCSI cable is configured to be ultra-thin and flexible and is designed to handle high bandwidths and support longer cabling distances, relative to conventional SCSI cabling.

Abstract: A bias compensator circuit for significantly reducing an offset produced by a termination bias that is associated with a differential pair bus. The differential pair bus is connected to a driver. The bias compensator circuit includes: (a) a signal source connected to a first line of the differential pair; (b) a first switch for switching ON the signal source while the driver is driving; (c) a signal sink connected to a second line of the differential pair; and (d) a second switch for switching ON the signal sink while the driver is driving.

Abstract: An integrated circuit with boundary scan includes core circuitry having at least one system data output. Boundary scan logic is used to control the integrated circuit to operate in a test mode or in a system mode. The boundary scan logic includes a test data line, a shift signal line, and a mode signal line. At least one output boundary scan cell having a boundary scan multiplexer is provided. The boundary scan multiplexer includes a control input coupled to the shift signal line, a first input coupled to receive a system data signal, and a second input coupled to the test data line. The boundary scan cell further includes a first output data register having an input coupled to an output of the boundary scan multiplexer. At least one output cell including an output data multiplexer is also included. The output data multiplexer includes a control input coupled to the mode signal line and includes as inputs the system data output line and an output of the first output data register.

Abstract: Disclosed is a host adapter having automatic termination, and a method for implementing the automatic termination. The host adapter includes a first connector for connecting to at least one external peripheral device and a second connector for connecting to at least one internal peripheral device. The host adapter further includes a termination system circuit that is coupled between the first connector and the second connector. The termination system circuit is configured to produce bit data that is indicative of whether a peripheral device is coupled to one or both of the first connector and the second connector. Preferably, the termination system circuit communicates the bit data to a software termination engine upon boot-up to enable or disable a termination of the host adapter. Furthermore, the termination system circuit includes a termination control decoder and a tri-state buffer.

Abstract: A semiconductor processing system, such as a system for scrubbing both sides of a wafer at the same time, that includes a brush box containment apparatus for use with highly-acidic or other volatile chemical solutions, a roller positioning apparatus and a (brush) placement device.

Abstract: A method of optical proximity correction. A main pattern is provided. The main pattern has a critical dimension. When the critical dimension is reduced to reach a first reference value or below, a serif/hammerhead is added onto the main pattern. When the critical dimension is further reduced to a second reference value or below, an assist feature is added onto the main pattern. The corrected pattern is then transferred to a layer on wafer with an improved fidelity.

Abstract: Disclosed is a low power scan flop cell design for enabling low power scan mode testing and reduced heat dissipation. The low power scan flop therefore enables "at speed" testing in scan mode, which enables comprehensive testing of high speed timing faults. The scan flop cell embodies a scan cell that has inputs that include a data input pin, a scan input (SI) pin, a scan enable (SE) input, and a clock input. The scan cell has outputs that include a Q' output and an NQ' output. The scan flop cell further includes a first logic gate having a Q output, a first input pin that is connected to the Q' output of the scan cell, and a second input pin. The scan flop also includes a second logic gate having an NQ output, a first input pin that is connected to the NQ' output of the scan cell, and a second input pin. An electrical interconnection is formed between the scan enable input of the scan cell and the second input pin of both the first logic gate and the second logic gate.

Abstract: Disclosed is an electrostatic discharge protection transistor having low input capacitance and method for making the same. The electrostatic discharge protection transistor includes a semiconductor substrate having a diffusion well and a source that is defined in the diffusion well. Further included is a drain that has a first sidewall, a second sidewall, and a lower diffusion floor. The first sidewall is located proximate to a channel region that lies between the source and the drain. Also, a polysilicon gate is disposed over the surface of the semiconductor substrate such that the polysilicon gate is defined between the source and the drain. Wherein the first sidewall of the drain is defined in the diffusion well and the lower diffusion floor of the drain is defined outside of the diffusion well and inside the semiconductor substrate.

Abstract: Disclosed is a temperature controlled dispense arm for dispensing chemicals in a spin coating machine. The temperature controlled dispense arm has a cooling portion containing cooling coils and a dispense arm base having chemical dispense passages. The temperature controlled dispense arm maintains the chemical dispense passages at a cooled temperature as determined by the cooling coils located in the cooling portion.

Abstract: The present inventions provide a high-speed serial data cable assembly with improved electromagnetic performance. In one embodiment, the high-speed serial data cable assembly includes a first connector, a second connector, a cable portion, and a capacitor. The first connector includes a conductive housing and a first plurality of pins, one of the first plurality of the pins being a ground pin. The second connector includes a conductive housing and a second plurality of pins. The cable portion includes a shield, the cable portion electrically coupling the first plurality of pins to the second plurality of pins, and the shield electrically coupling the ground pin of the first connector to the conductive housing of the second connector.

Abstract: Disclosed is a system for processing a semiconductor wafer through plasma etching operations. The system has a process chamber that includes a support chuck for holding the semiconductor wafer and a pair of RF power sources. In another case, the system can be configured such that the electrode is grounded and the pair of RF frequencies are fed to the support chuck (bottom electrode). The system therefore includes an electrode that is positioned within the system and over the semiconductor wafer. The electrode has a center region, a first surface and a second surface. The first surface is configured to receive processing gases from a source that is external to the system and flow the processing gases into the center region. The second surface has a plurality of gas feed holes that are continuously coupled to a corresponding plurality of electrode openings that have electrode opening diameters that are greater than gas feed hole diameters of the plurality of gas feed holes.

Abstract: The present invention provides a precharge circuit for precharging bit lines coupled to a read sense amplifier and a RAM cell. The precharge circuit includes a set of precharge transistors, a first transistor, and a transistor pair. The set of precharge transistors is coupled to said bit lines for precharging said bit lines with one precharge transistor per bit line. The first transistor is coupled to turn on said set of precharge transistors when said RAM cell is not being read. The first transistor is operative to reduce the gate-to-source voltage V.sub.GS of said set of precharge transistors such that each of said precharge transistors output a reduced precharge voltage to the associated bit line. The transistor pair is coupled to said set of precharge transistors and is operative to switch said precharge transistors for reading said RAM cell. In this configuration, the RAM cell outputs a differential signal onto said bit lines when said precharge transistors are turned off.

Abstract: A computer system incorporating an apparatus for allocating exclusive shared resource requests includes a shared resource, a first type device coupled to the shared resource and a second type device coupled to the shared resource. The computer system also includes an arbitrator unit coupled to the shared resource capable of granting the second type device exclusive access to the shared resource by preventing the first type device from being granted exclusive access to the shared resource. The arbitrator unit prevents the first type device from being granted exclusive access to the shared resource for at least a duration of time after the second type device has completed an associated second type shared resource transaction.

Abstract: An RF tag has an enable/disable circuit connected to a critical part of an electronic object/circuit, e.g. a computer mother board. The critical part of the circuit is any circuit component and/or connection that can enable and/or disable the electric circuit operation. Signals are sent to the tag to change data in the tag memory which causes the enable/disable tag circuit to control the critical part to enable and disable the electric circuit. A system checks the status of the tag, e.g. the electronic circuit was paid for, before enabling the electronic circuit.

Abstract: Disclosed is a method for reducing faceting of a photoresist layer during an etch process. The method includes depositing a metallization layer on a semiconductor substrate, and forming a photoresist layer over at least a portion of the metallization layer. The method also includes treating the photoresist layer with a first plasma so as to harden the photoresist layer against a metal etching plasma. The method further includes exposing the metallization layer and the photoresist layer to the metal etching plasma. The metal etching plasma etches the metallization layer at a substantially faster rate than the treated photoresist layer so that faceting on the photoresist layer is substantially reduced.

Abstract: Disclosed is a method for booting a computer system. The computer system includes a first device and a second device which, during initialization of the computer system, are each respectively automatically associated with a unique identification used in a computer generated request to indicate whether the first device or the second device is to respond to the computer generated request. The method includes the act modifying each unique identification that is associated with the first device and the second device of the computer system. In this manner, the second device responds to the computer generated request for the first device, and the first device responds to the computer generated request for the second device.

Abstract: A system for preparing a skinned food product includes a roasting unit, a smoking chamber, and a conveyor system for transporting the skinned food product through the roasting unit and through the smoking chamber. The roasting unit has a heated zone for at least partially loosening the skin of the skinned food product. The heat in the heated zone may also blacken portions of the skinned food product. The conveyor system rotates the skinned food product as the product passes through the heated zone. The contact with the smoke in the smoking chamber provides the skinned food product with a desired flavor. A method for preparing a skinned food product includes contacting the product with heat to at least partially loosen a skin thereof, and contacting the product with smoke for a period of time sufficient to provide the product with a smoked flavor. The system and method may be used to prepare skinned food products such as tomatoes, peppers, onions, garlic, corn, potatoes, and artichokes.

Abstract: A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.