Abstract: Disclosed is a method and apparatus for establishing communication to a remote peripheral device over a network. The method includes issuing a request to use a peripheral device to a remote communications dynamically linked list, and determining whether the peripheral device is a local peripheral device or a remote peripheral device. The method further includes sending the request over a network to a remote computer that has a server application when the peripheral device is the remote peripheral device. The server application is configured to enable sharing of peripheral devices that are connected to the remote computer. Preferably, the system registry of the computer making the request is altered to enable efficient communication with the remote peripheral device.

Abstract: An improved network interface card (NIC) allows received ATM cells of a protocol data unit (PDU) to be grouped by a programmable size and then sent via an efficient DMA transfer to the host computer memory. Sizes of the blocks of data transferred from the NIC to the host memory are optimized for virtual circuit type, PDU type, NIC memory constraints, bus bandwidth, maximum DMA transfer rate, etc. A destination host receives cells for multiple virtual circuits in an interleaved fashion for various PDUs. The received cells are divided up by virtual circuit; cells for one virtual circuit are stored in a linked list of slots, where each slot contains one ATM cell. Cells from each virtual circuit are linked together in a group, with a separate linked list of cells for each virtual circuit. A programmable group size parameter defines how many cells are grouped together in the linked list before the group is dispatched to system memory in the host computer.

Abstract: A dual sided slot valve is in a vacuum body between adjacent process and transport modules. Separate valves are provided for each of two valve body slots, one body slot being separately closed or opened independently of the other. The separate valves allow a vacuum in the transport module while an adjacent process module is open to the atmosphere for servicing. The valve allows access to an open valve for servicing the open valve in that one actuator motor stops the valve in an open, but not vertically-spaced, position relative to the respective slot. The open valve is more easily reached by a gloved hand of a service worker. A separate actuator motor moves the valve vertically down from the open position and away from the slot to expose the sealing surface around the slot for cleaning. The vertical distance of the vertically-moved valve from an access opening makes it difficult for the worker's glove to reach the valve for service.

Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer.

Abstract: The present invention describes a method of cleaning a substrate wherein the substrate is placed into a first brush station while a chemical solution is delivered to the first brush station at a desired cleaning level. The substrate is then scrubbed in the first brush station. After the substrate is scrubbed in the first brush station the substrate is transferred to a second brush station. The chemical solution used in the first brush station is then delivered to a brush in the second brush station in a ramp up manner in order to clean the brush in the second brush station. The delivery of the chemical solution to the second brush station is then stopped and deionized water is delivered to the second brush station. The substrate is then scrubbed using the deionized water in order to rinse the chemical solution from the substrate prior to transferring the substrate from the second brush station to another processing station.

Abstract: The present invention provides an apparatus for generating an error locator polynomial from a plurality of partial syndromes. The partial syndromes are generated from a data sector sequentially read from a storage medium. The apparatus comprises discrepancy circuitry, correction polynomial circuitry, connection polynomial circuitry, and a control circuitry. The discrepancy circuitry is configured to receive a selected partial syndrome for generating a discrepancy .DELTA..sup.(k). The correction polynomial circuitry is configured to receive the kth discrepancy .DELTA..sup.(k) from the discrepancy circuitry for generating an associated correction polynomial T(z). The connection polynomial circuitry is configured to receive the kth discrepancy .DELTA..sup.(k) from the discrepancy circuitry for generating an associated connection polynomial .LAMBDA..sup.(k) (z).

Abstract: A position detector is provided for use on a spin-drying machine employed in integrated circuit (IC) fabrication to detect whether the spin-drying machine has shifted in position during operation. If the spin-drying machine is positioned incorrectly, the position detector is capable of stopping the operation of robot arms used to grab and position wafers on the spin-drying machine so that the robot arms will not be damaged or crash into the wafers on the spin-drying machine due to the incorrect positioning of the spin-drying machine. The position detector is designed for use on a spin-drying machine having a spinning unit, a fixed platform surrounding the spinning unit, and at least one robot arm mounted on the fixed unit. The position detector comprises a pair of emitters mounted on the spinning unit and a pair of oppositely arranged receivers on the fixed platform.

Abstract: An improved file system and method for incrementally recording data on compact discs is disclosed. The improved file system and method employs compact discs physically formatted in accordance with the so-called Orange Book specification. Files to be stored are selected from time to time and are divided into packets. The packets are then recorded in a program area of the compact disc together with link, run-in and run-out blocks in a format compatible with the Orange Book rules for linking incrementally recorded packets. File linking information is also stored with each file. If desired, files may, but need not, be recorded in a form compatible with existing CD-ROM and drivers adhering to the ISO-9660 standard. As selected files are recorded, file and directory information are stored in a first storage area either in a host system or in a track of the compact disc in a double linked and highly efficient format.

Abstract: Disclosed are methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer. The semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, and an oxide material that covers a top surface of the polysilicon gate electrodes of the transistor devices. A silicon nitride layer is also disposed over the semiconductor devices and a dielectric layer is disposed over the silicon nitride layer. The method includes depositing a silicon nitride layer over the dielectric layer, and etching nitride windows in the silicon nitride layer to expose the dielectric layer where conductive contacts to selected polysilicon gate electrodes are desired. The method then includes pattering a photoresist mask over the silicon nitride layer.

Abstract: A chemical-mechanical polishing station for polishing wafers. The polishing station comprises a slurry supplier, a polishing pad capable of collecting the slurry, and a polishing head capable of rotating a wafer and lowering the wafer onto the polishing pad in contact with the polishing pad and the slurry during a polishing session. The polishing head further includes a retaining ring for positioning the wafer. The retaining ring houses a light-emitting device capable of shining a beam of light onto the slurry and a light sensor for picking up the beam of light reflected back from the slurry. The exact polishing end-point can be decided by analyzing signals obtained from the light sensor.

Abstract: Disclosed is an integrated circuit chip having an improved ESD protection structure. The integrated circuit chip includes a core logic region having a plurality of transistor devices that are interconnected to form a specific integrated circuit device. A plurality of input/output cells are defined along a periphery of the integrated circuit chip. An ESD bus die edge seal that defines a single ring around the periphery of the integrated circuit chip is provided. The ESD bus die edge seal is positioned outside of the plurality of input/output cells closest to a physical outer edge of the integrated circuit chip. Further, a plurality of (Vss) supply cells are contained in selected ones of the plurality of input/output cells. And, a plurality of ESD cross-coupled diodes are connected between the plurality of (Vss) supply cells and the ESD bus die edge seal.

Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded.

Abstract: An end effector has a tower with non-stacked spatulas. Tolerance stacking is avoided by making grooves in the tower relative to a common reference surface, and mounting the spatulas in such grooves. The grooves are provided in separate planar walls of the tower. The walls intersect to enhance the structural properties of the tower. The tower has a dual-purpose clamp formed integrally with one wall for use in assembling the tower and the spatulas, and for mounting the completed end effector in a load lock. The spatula may carry a wafer during various operations, e.g., semiconductor processing, material deposition and etching systems, or in flat panel display processing systems. The carrying of the wafers is notwithstanding vibration of equipment for performing the manufacturing operations, which vibration is primarily in a range of frequencies.

Abstract: A low power bank architecture implemented in memory access circuitry is disclosed. The bank architecture includes a bank circuit that has a bank core integrated with a pair of bitlines and a bank interface circuit that is coupled to the pair of bitlines. The bank architecture further includes a global data bus pair that is configured to communicate a less than full rail voltage swing. The global data bus pair is coupled to the bank interface circuit of the bank circuit that is designed to convert the less than full rail voltage swing into an up to about full rail voltage swing that is communicated to the pair of bitlines. The bank circuit is configured to be replicated once for each of the pair of bitlines in a memory core having an array of bank cores. By communicating memory access signals, such as differential write data, at a less than full rail voltage over the global data bus pair, a substantial amount of power is saved, which provides excellent power savings for many electronic device applications.

Abstract: A system and method for using the optional staging of files to a hard disk and a method for packetizing data to efficiently utilize the available storage capacity of a CD-R disc, and allows writes to and reads from an open CD-R disc while reserving a track to be written with a compatibility hierarchy for a conventional CD-ROM file system when the CD-R disc is closed.

Abstract: A photolithography technique. A chip has latitudinal scribe lines and longitudinal scribe lines and also has a plurality of alignment marks. The latitudinal scribe lines and longitudinal scribe lines divide the chip into a plurality of dies. Some dies are effective dies. Alignment marks are located at each intersection of the latitudinal and longitudinal scribe lines. Each shot contains a plurality of dies. A mask having a plurality of mask alignment marks is provided. The mask alignment marks are used for alignment with alignment marks in the chip. The alignment marks of the chip are aligned with the mask alignment marks of the mask. At least three alignment marks close to the effective dies in the shots are selected for detection a focus and focal plane of each shot, so as to level the shot and perform an exposure step on each shot, shot by shot.

Abstract: Improved methods and apparatus to facilitate switching Asynchronous Transfer Mode (ATM) cells through an ATM switching circuit are disclosed. The improved methods and apparatus facilitate the implementation of per virtual connection buffering, per virtual connection arbitration of ATM cells, and/or per virtual connection back-pressuring to improve switching efficiency and/or reduce the complexity and/or costs of the ATM switching circuit.

Abstract: A boot sequence adapted for use with a computer system during execution of system BIOS. The computer system includes a random access memory (RAM), a selected number of controllers. Each of the controllers reside in a respective expansion slot (e.g., PCI slot), have at least one drive associated therewith, and have an option read only memory (Option ROM) that includes a BIOS initialization code and a runtime code.

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer.

Abstract: Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide (IMO) layer over the first metal layer and forming a via in the IMO layer such that the via exposes a portion of the first metal layer and a side wall of the via in the IMO layer. The method also includes conformally forming a first barrier layer over the IMO layer and the via such that a portion of the first barrier layer is deposited over the side wall of the IMO layer and the exposed portion of the first metal layer. The method further includes depositing a second metal layer over the first barrier layer such that the second metal layer fills the via within the first barrier layer portion deposited in the via to form a metal via.