Abstract: A system and method for performing 3D graphics copying operations in such a manner as to produce both a smooth image and smooth edges. The alpha value of each pixel is used to mark the pixels which are and are not part of the image to be copied, and removes unwanted pixels from bilinear filtering operations. After filtering, the resultant alpha values along the edges of the object are used to eliminate unwanted pixels, and to blend the object into the background of the image, which reduces or eliminates the "blocky" edges.

Abstract: A method for fan-folding lithium-ion-polymer battery cells, wherein gaps are left in the active material at fold locations of the metallic backing conductor. This avoids fatigue at the fold locations when the active materials expand and contract during charge and discharge.

Abstract: The integrated circuit comprises a central processing unit, a program memory containing a program of instructions connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory, the instructions being carried out by the central processing unit, and at least one data memory connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory. The circuit comprises breaking means enabling the defining of a combination of conditions pertaining to the values present on two of the buses of the memories and to the values of the control signals for access to at least one of these memories, and halting the performance of the instructions if these conditions are verified. The disclosed device is especially valuable for testing an application program of the integrated circuit.

Abstract: A graphics processing system with a message-passing architecture, in which the rasterizer can be bypassed by a particular type of message from the host. This permits rasterization to be slaved to the host downloads and bitmasks, so that images and patterns can be applied to lines and polygons, rather than just rectangles as is the case for prior art.

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.

Abstract: A graphics subsystem in which a very fast clear operation is performed without the need to address each pixel, and without using memories which include a hardware fast-clear capability. This is implemented by using a reference frame counter: the window is divided up into n regions, where n is the range of the frame counter (i.e. n=2.sup.p, where p is the number of bits in the frame counter). Every time the application issues a clear command, the reference frame counter is incremented (and allowed to roll over if it exceeds its maximum value), and only the n.sup.th region is cleared. The clear updates the depth and/or stencil buffers to the new values and the frame count buffer with the reference value. This region is much smaller than the full region the application thinks it is clearing, so takes less time and hence gives the speed increase. When the local buffer is subsequently read and the frame count is found to be the same as the reference frame count, the local buffer data is used directly.

Abstract: The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.

Abstract: A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.

Abstract: A process for making a package for discrete semiconductor devices, wherein the insulating characteristics of the package are increased by introducing cuts, grooves and positioning holes in the metal plate and shaping in the retractable positioning pins of the metal plate in the molding die.

Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (A1) and being of the type comprising first memory, circuit (DM) designed to be accessed by means of address for containing user data, second memory circuit (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (A1) and the data input (DI) a writing address and user data respectively and to generate error data and to write, the data in the first circuit (DM) and second circuit (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to the data output (DO) and characterized in that the second, circuit (EM) is the type designed to be accessed by means of content and, the c

Abstract: Integrated circuits can have both a microprocessor and an internal read-only memory of programs on one and the same chip. To facilitate the perfecting and finalizing of the programs of the read-only memory without undertaking the manufacture, for the perfecting and finalizing operation, of a special version of the circuit that is far too different from the definitive version, an external memory is used for the perfecting and finalizing operation. A contact pad of the chip is used for the transmission, in series mode, of a program coming from an external memory. A mode selection pad makes it possible to define whether the microprocessor must work in internal ROM mode (the normal mode) or in external ROM mode (the mode for the perfecting and finalizing operation).

Abstract: In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder during a determined duration. The filtering signal is applied more particularly to the row decoder which selects a row corresponding to an address applied to the input of the decoder and applies a control voltage to this row. This method is particularly advantageous in low-voltage memories.

Abstract: An electronic computation circuit comprises a multiplication operator with a serial input, a parallel input and a serial output, a first register connected by its output to the parallel input of the operator, a second register connected by its output to the serial input of the operator, a third register and a multiplexing circuit to selectively connect at least one data input terminal and the output of the operator to the inputs of the first, second and third registers, and to produce the output of the electronic multiplication circuit. Application to the operations of multiplication, squaring, exponentiation and modular inversion on a finite field denoted GF(2.sup.n).

Abstract: A graphics subsystem which permits single buffered windows to exist in a double buffered system. Thus ALL the pixels on the screen are ultimately double buffered, but the single buffered should not appear to be double buffered. To support the single buffered windows, certain write operations are modified to write the same half-word of data into both the front and back half-words of an addressed location. This permits non-double buffered windows to remain correct when the RAMDAC.TM. is manipulated to swap buffers.

Abstract: In order to make it possible to ascertain that the programming cycles in an EEPROM type memory have been carried out efficiently, supplementary test cells are provided. A data writing operation is carried out in three successive cycles that consist in the programming of a test cell with a first logic value, a second cycle for the programming of the data elements and a third cycle for the programming of the test cell with a logic value that is complementary to the first one. The state of the test cell enables the detection of power interruptions during programming.

Abstract: A parking citation issuing and enforcement system including an electronic citation writing device and an electronic parking meter. The system includes means whereby data, such as the status of the meter, may be transmitted between the electronic citation writing device and the electronic parking meter. The system also includes the ability to download the data from the electronic citation writing device to a computer for reporting of the citation data as well as the data retrieved from the electronic parking meter. This data cannot be manipulated while in the meter, during transmission to the electronic citation writing device, or during and after uploading to computer. Therefore, the report generated can be used in court to help resolve parking violation disputes.

Abstract: A multiplication circuit having a Booth decoder, a partial product generator and a computation and formatting circuit. An incrementing device is combined with the computation circuit, enabling an anticipated incrementation if it is desired to obtain a rounded result.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: Distortion control in a push-pull output stage of a speech amplifier of a telephone powered through the telephone line is more effectively and advantageously implemented by independently sensing an eventual state of saturation reached by any of the two output transistors of the amplifier, summing the current signals representative of the sensed state of saturation of either or both output transistors, integrating the resulting sum current signal to produce a DC signal and using the DC signal for activating an AGC loop. The DC signal indiscriminately accounts for any cause of saturation, though virtually representing the level of the amplified AC signal. Distortion may be controlled without penalizing output voltage swing and power consumption.

Abstract: A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.