Patents Represented by Attorney Matthew Anderson
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Patent number: 5732012Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.Type: GrantFiled: March 17, 1994Date of Patent: March 24, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Paolo Cappelletti, Silvia Lucherini, Bruno Vajana
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Patent number: 5727192Abstract: A device and method for providing a frame buffer interface to a serial rendering system which automatically synchronizes with data in the rendering path before blanking the active frame. To prevent rewriting to a frame buffer of rendered data before the current rendered data can be displayed, the disclosed embodiment provides that when the data is ready to be displayed, all further writes to the buffer are suspended, while all other accesses throughout the system are allowed to proceed. When the vblank command is received, data is passed to the display system for display, and writes to that buffer are re-enabled. When writes to a specific buffer portion are suspended, all other processes may continue independently.Type: GrantFiled: May 1, 1996Date of Patent: March 10, 1998Assignee: 3DLabs Inc. Ltd.Inventor: David Robert Baldwin
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Patent number: 5715204Abstract: The differential input stage of a sense amplifier is provided with a positive feedback for introducing a predefinable hysteresis that will prevent spurious transitions of the output of the sense amplifier, enhancing noise immunity. The positive feedback is realized by employing an inverting amplifying stage, which will introduce an hysteresis on one of the two switching phases. The thresholds of the sense amplifier may be made symmetric by modifying the area ratio of the load transistors.Type: GrantFiled: May 2, 1995Date of Patent: February 3, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventor: Antonio Barcella
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Patent number: 5714899Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.Type: GrantFiled: January 6, 1997Date of Patent: February 3, 1998Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Sylvie Wuidart, Tien-Dung Do
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Patent number: 5710934Abstract: Methods and test platforms for developing an application-specific integrated circuit incorporating, on the same chip, a signal processor core, RAM memory and ROM memory intended to receive a management program and processing program, and input-output management peripherals specific to the application. The signal processor, RAM memory and ROM memory correspond respectively to existing separate IC components. The processing program is developed and tested on a test platform including at least these separate IC components together with a core-emulation integrated circuit, which includes the signal processor core in a minimal configuration. An interface program and diagnostic interface logic allows the platform to be controlled from a microcomputer, which can thereby implement automatic chaining of tests.Type: GrantFiled: May 15, 1995Date of Patent: January 20, 1998Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Mariano Bona, Pierre-Albert Comte, Duc Pham-Minh
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Patent number: 5710729Abstract: An oversampling digital filter with Finite Impulse Response is implemented using a serial structure having a memory for the coefficients, a memory for the signal samples to be filter, a multiplier connected to the output of the memories, an accumulator connected to the output of the multiplier, and a simple control unit which controls these elements according to an input clock signal.Type: GrantFiled: May 31, 1995Date of Patent: January 20, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Sandro Delle Feste, Marco Bianchesi, Alessandro Cremonesi
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Patent number: 5710739Abstract: A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.Type: GrantFiled: June 6, 1995Date of Patent: January 20, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Cristiano Calligaro, Roberto Gastaldi, Paolo Rolandi, Guido Torelli
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Patent number: 5707884Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.Type: GrantFiled: June 1, 1995Date of Patent: January 13, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Gabriella Fontana, Orio Bellezza, Giuseppe Paolo Crisenza
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Patent number: 5708451Abstract: Nonuniformities of luminance characteristics in a field emission display (FED) are compensated pixel by pixel by storing a matrix of correction values, determined by testing, and by applying a corrected drive signal through the relative column drive stages. The individual pixel's correction factor that is applied to the corresponding video signal may be stored in digital or analog form in a nonvolatile memory array. Various embodiments are described including the use of a second updatable RAM array wherein pixel's correction factors are calculated and stored at every power-on to provide an opportunity of trimming-up the luminance of the display for compensating long term decline of luminance due to the phosphors ageing process.Type: GrantFiled: July 22, 1996Date of Patent: January 13, 1998Assignee: SGS-Thomson Microelectronics, S.r.l.Inventor: Livio Baldi
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Patent number: 5701444Abstract: A rendering subsystem with enhanced capability for handling both 2D rendering and 3D rendering tasks. Since the 2D rendering tasks may be generated by the operating system (or other user-interfacing software), it is highly desirable not to interfere with rapid performance of 2D rendering, even if substantial 3D rendering tasks have been loaded into the pipeline. To avoid this, the innovative system uses dual independent contexts, and suspends 3D rendering operation during periods of 2D rendering demand. Moreover, a certain percentage of cycles is reserved, as a minimum, to be available for 2D operations if any have been requested. Window ownership identifiers are maintained for each pixel, but these identifiers are only updated when the 3D rendering operations have been suspended. Moreover, the window position (offset) values are only updated during periods when 3D rendering has been suspended.Type: GrantFiled: March 24, 1995Date of Patent: December 23, 1997Assignee: 3dLabs Inc. Ltd.Inventor: David Robert Baldwin
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Patent number: 5696457Abstract: A low-voltage transconductor circuit in which the common mode gain of a first transconductor stage is compensated by a second transconductor stage (connected in parallel with the first transconductor stage) which has no differential mode transconductance, and which is connected so that its common mode transconductance offsets the common mode transconductance of the stage. This greatly reduces the common mode current signal at the output, while avoiding the necessity for a current sink at the source of the input transistors.Type: GrantFiled: May 31, 1995Date of Patent: December 9, 1997Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Francesco Rezzi, Andrea Baschirotto, Rinaldo Castello
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Patent number: 5694175Abstract: A method for the recognition of video standards, in which an up/down counter is used to detect the polarity of synchronization pulses. Specifically, a value representing a duration is memorized, a counting value (Q) is produced, this value being incremented when a binary synchronization signal (INCI) is in one state and decremented when this signal is in the other state, a comparison is made of the value representing the duration and the counting value, at a given time, of the synchronization signal, and a signal representing the standard is produced as a function of the result of the comparison. This method is implemented by a circuit comprising a microcontroller, a detection circuit producing a pick-up control logic signal (CAP), a counter producing a counting value (Q) and a register to load the counting value when the pick-up control signal is active.Type: GrantFiled: February 24, 1995Date of Patent: December 2, 1997Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Frederic Gaigneux, Yong-Uk Lee
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Patent number: 5684425Abstract: Electronic switch for low-voltage supply circuits completed with CMOS technology and comprising a first, a second and a third circuit element (SW1 ,SW2,SW3) consisting each of a pair of complementary transistors. The first and second of said elements (SW1,SW2) are inserted between two connection terminals of the switch (A,B) while the third element SW3 is inserted between a node (C) included between the first and the second element of a voltage reference (VCM). The first and second element are driven to conduction in phases (.phi.1) not overlapping the phases (.phi.2) in which it conducts the third element.Type: GrantFiled: February 27, 1995Date of Patent: November 4, 1997Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Germano Nicollini, Pierangelo Confalonieri
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Patent number: 5682349Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.Type: GrantFiled: May 31, 1995Date of Patent: October 28, 1997Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Giovanni Campardo, Emilio Camerlenghi
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Patent number: 5679587Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.Type: GrantFiled: May 31, 1995Date of Patent: October 21, 1997Assignee: Consorzio per la Ricerca sulla Microelettronica nel MezzogiornoInventor: Raffaele Zambrano
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Patent number: 5678834Abstract: A tool to aid in adjusting the position of a tandem rig under a trailer. The tool attaches to the tandem, where it can be adjusted to apply a force to the handle which unlocks the positioning pins. This allows adjustments to the position to be made without the need to walk back and check the tandem to see if the positioning pins have been freed from their locked position.Type: GrantFiled: March 6, 1996Date of Patent: October 21, 1997Assignee: GSW EnterprisesInventor: Glenn Wise
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Patent number: 5680353Abstract: Electrically programmable memories, in particular EPROMs, generally have an internal signature which can be read by the memory-programming device. This internal signature indicates the origin of the part (manufacturer's identification) and the appropriate programming mode for the part (fast programming, "intelligent" programming, etc.). Here, it is proposed that this information be recorded in a UPROM (unerasable programmable read-only) memory, i.e., in practice an EPROM memory masked by a layer of aluminium which prevents its erasure by ultraviolet rays.Type: GrantFiled: September 3, 1993Date of Patent: October 21, 1997Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Jean-Marie Gaultier, Bertrand Conan, Augustin Farrugia
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Patent number: 5675539Abstract: An integrated circuit memory that contains a device for the precharging and reading of the bit lines, including a precharging element, a current-voltage converter and a read circuit, further contains a test circuit to isolate the output of the converter from the precharging element and from the read circuit, to apply a test voltage to a cell of the memory through the converter and to measure the current in the cell.Type: GrantFiled: December 21, 1995Date of Patent: October 7, 1997Assignee: SGS-Thomson Microelectronics, S.A.Inventors: Jean-Michel Mirabel, Emilio Yero
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Patent number: 5666115Abstract: The invention relates to a shifter stage for a variable-length digital code decoder which decodes one code per clock cycle, reads input data arriving from a memory, supplies a logical unit on each cycle with a word having the size of the longest variable-length code to be decoded, receives from the logical unit the number of bits of the code decoded on the preceding clock cycle, and effects a shift in the data read equal to the cumulative total of the lengths of codes decoded since the last read of input data.It comprises a first barrel shift register (11) which reads the input data and performs a shift in the data read equal to the cumulative total of the lengths of the codes decoded between the preceding cycle and the start of the last read, and a second barrel shift register (13) which receives the data arriving from the first register and performs a shift equal to the length of the code decoded on the preceding cycle.Type: GrantFiled: February 6, 1995Date of Patent: September 9, 1997Assignee: SGS-Thomson Microelectronics, S.A.Inventor: Oswald Colavin
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Patent number: 5659516Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.Type: GrantFiled: January 3, 1995Date of Patent: August 19, 1997Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Giulio Casagrande, Emilio Camerlenghi