Abstract: In a switching converter that delivers power to a load, a transition between higher load and lower load modes is controlled by varying the width of switch control pulses in one operating phase and blanking individual pulses in another operating phase. Alternatively, in yet another operating phase the time interval between switch control pulses is varied and, at a given load condition, the time interval between successive pulses remains essentially constant.

Abstract: An arithmetic and logic computation device having an arithmetic and logic unit with a shifter on at least one input. The computation device, which includes a multiplier, propagates a carry and applies a carry to the multiplier to carry out double precision multiply and multiply-accumulate operations.

Abstract: The integrated circuit memory has a matrix of cells and a plurality of circuits enabling the selective application, to the cells, of programming and erasure potentials. These circuits are controlled by an integrated state machine programmed to perform algorithms adapted to the operations to be performed. In order to facilitate the devising and perfecting of these algorithms, the memory includes selection means enabling an external tester to be substituted for the state machine. A particularly advantageous application is in "FLASH EEPROM" memories.

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

Abstract: The disclosed device can be used to accelerate the tests carried out on memories by using a row and column address generator normally designed for operations of pre-erasure programming of the memory. The working in test mode is determined by a test word. During a test, row and/or column counters of the generator are selectively incremented by an incrementation signal given by a control unit that performs a pre-erasure programming operation. Application notably to FLASH EEPROM memories and the integrated circuits that incorporate these memories.

Abstract: In order to give the current the quality of low sensitivity to temperature, a first MOS transistor and a second MOS transistor supplied by a current mirror have their sources connected to the ground, with the drain and the gate of the first transistor being connected to the gate of the second transistor by means of a resistor. The quotient of the dimensional ratios of the transistors is equal to the coefficient of the current mirror and the transistors are doped so that the threshold of the second transistor is greater than that of the first one. Application notably to ramp generators for the programming of EEPROM cells.

Abstract: A power supply for a computer system having at least one energy demanding component. The power supply includes a transformer having a primary side coupled to an AC main and a secondary side coupled to an output line, a charging circuit coupled between the secondary side of the transformer and the output line, an optical switch coupled to the secondary side of the transformer and comprised of an optical transmitter and an optical receiver, a secondary side power switch coupled to the optical receiver, a pulse width modulator coupled to an output of the optical receiver and a transformer switch coupled to an output of the pulse width modulator. The pulse width modulator generates a pulse sequence which alternates between first and second states, each having respective durations and frequencies. At each change between the first and second states, the transformer switch selectively connects or disconnects the primary side of the transformer with the input line.

Abstract: An initialization circuit for memory registers, having a signal input being applied a supply voltage which rises linearly from a null value, and an initializing output connected to an input of a memory register and on which a voltage signal, being equal or proportional to the supply voltage, during the initialization step, and a null voltage signal, upon the supply voltage dropping below a predetermined tripping value, are produced. Additionally, the circuit has, between the input and the output, a first circuit portion connected to the input; a second circuit portion connected after the first and having a first output connected to the initializing output; and a third, inverting circuit portion having an input connected to a second output of the second portion and an output connected to the first portion to hold off that first portion while the supply voltage drops below the threshold voltage.

Abstract: An internal AC adapter which incorporates a space efficient EMI filter is positioned within a main chassis portion of a portable personal computer having at least one energy-demanding component also positioned within the main chassis portion. The internal AC adapter, which converts alternating current received from an alternating current main to direct current for transmission to the energy-demanding components, includes a first connector for electrically connecting the internal AC adapter to the alternating current main, a bridge rectifier circuit having an AC input side electrically connected to the first connector and a DC output side and a space efficient electromagnetic interference filter having an input side electrically connected to the DC output side of the bridge rectifier circuit and an output side. The bridge rectifier circuit converts alternating current received from the first connector to direct current for transmission to the electromagnetic interference filter.

Abstract: A power supply for a computer system includes a transformer having a primary side coupled to an AC main and a secondary side coupled to an output line, a charging circuit coupled between the secondary side of the transformer and the output line, an optical switch coupled to the secondary side of the transformer and comprised of an optical transmitter and an optical receiver, a secondary side power switch coupled to the optical receiver, a short circuit protection circuit coupled to the charging circuit, the output line and the optical receiver, a pulse width modulator coupled to an output of the optical receiver and a transformer switch coupled to an output of the pulse width modulator. The pulse width modulator generates a pulse sequence which alternates between first and second states, each having respective durations and frequencies. At each change between the first and second states, the transformer switch selectively connects or disconnects the primary side of the transformer with the input line.

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1 , M2) together with vertically-conducting bipolar junction transistors transistors (T1, T2). These IGBT transistors are laterally conducting, having drain terminals (9, 19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1, T2) of the bipolar type.

Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.

Abstract: A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

Abstract: In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches.

Abstract: A data processing and memory system for transferring data elements page-by-page between several memories and modifying the data elements in the first memory. In order to reduce the set-up time when generating a new image, the processor stores the background color of the image for each new page. Then, when each new page is transferred to one of the memories, the background color is repeated for each data-element in the page.

Abstract: To provide efficient protection, in reading mode, of the stored data elements, the integrated circuit has an EEPROM type memory and a lock (L) protecting the zone of the memory. The memory contains a read-protected password (PW) and the circuit has means to release the lock (L) if the circuit receives a write command at the address of the password of the same encrypted password (PW). Application notably to electronic systems and instruments using confidential codes, such as car radios.

Abstract: A graphics processing system in which sub-pixel correction is implemented in a new and more economical way. A half-pixel offset is originally imposed on both the X and Y axes, so the sub-pixel correction value may be positive or negative. A relatively coarse resolution is used for subpixel correction, so that the DDAs (and other functional blocks) do not have to perform a full multiply: instead they merely perform simple add operations (addition of partial products) to derive the necessary offset from the delta-X values, using a proportionality constant provided by the rasterizer. The DDAs preferably include a "guard band" in their calculations, so that values which exceed the maximum (e.g. 255, for 8 bits of subpixel resolution) do not wrap to zero; instead the output is held at the maximum until the computed value comes down below the maximum.

Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

Abstract: An analog-to-digital converter (ADC), comprising an internal digital-to-analog converter (DAC), driven by a successive approximation register (SAR), and a comparator, is provided with a correction logic circuit that controls the execution of a verifying and correcting routine at the end of each conversion routine. Master-Slave cells that compose the SAR are provided with a dedicated circuitry, responding to said correction control circuit, for confirming, incrementing or decrementing the bit stored in the cell by at least an LSB. An extremely simple routine, performed at the end of each conversion cycle, allows correction of incorrectly converted digital data because of the occurrence of missing codes in the internal DAC. The corrector does not require the use of memories and/or analog circuits and is very cost- effective and permits a greatly improved production yield of complex devices containing ADCs.