Abstract: A data processing method is provided to enable a calculation based signal analyzer, such as an FFT based spectrum analyzer, to produce results corresponding to a swept spectrum analyzer employing a video bandwidth (VBW) filter. Once a spectrum is produced the frequency axis is replace by a corresponding time axis, so that a time domain filter, such as a video bandwidth (VBW) filter can be applied. The filter characteristics are applied by performing an FFT to produce frequency domain data, multiplying by the frequency response to produce a filtered version, performing an inverse FFT and replacing the time axis with the original frequency axis to produce a filtered version of the display spectrum data.

Abstract: A load testing apparatus and method has a display unit for the presentation of data that relate to a load test of a telecommunication network. The display includes a graphical user interface with the load test being divided into several test phases and on the graphical user interface functionalities being assigned to these test phases. The load testing apparatus further has a storage device into which user identifiers are enterable, and the functionalities are pooled into groups so that for each identifier there one or more groups of functionalities may be enabled.

Abstract: An up-converter 124 frequency-up-converts an analog signal Sm. A down-converter 121 frequency-down-converts analog signal Sm. A signal selection block 125 selects one of the frequency-up-converted signal Sfu and frequency-down-converted signal Sfd. The signal Se selected by the signal selection block 125 is provided to the primary winding of a transformer 127. A signal induced in the secondary winding of the transformer 127 is provided to an A/D converter 128 to produce a digital signal Dm. For example, if the analog signal Sm has DC or a low frequency close to DC, the signal Sfu is selected as the signal Se. If the analog signal Sm does no have DC nor a low frequency close to DC, the signal Sfd is selected as the signal Se.

Abstract: A linearity corrector is provided that reduces distortion in a signal processing system, such as an ADC. The linearity corrector provides a first order signal path having distortion components connected to an adder, and a filter product circuit that is also connected to the adder. A method is provided for reducing distortion by calculating a filter product and adding the filter product to a first order signal having a relative delay such that the filter product reduces, or eliminates, the order of distortions corresponding to the order of the filter product.

Abstract: A measurement instrument is provided with an FFT module providing a frequency domain output; and a power calculator connected to the frequency domain output to measure power statistics for a test signal of arbitrary length. In some embodiments, a spectrum integration module is provided to calculate the power contained within a frequency band. In an embodiment, a filter/averaging module is provided to compute signal power statistics over an arbitrary time period. Accumulators may be provided to store data related to maximum power, minimum power, average power, or peak to average power. A CCDF module may be provided in some embodiments to calculate CCDF related measurements. Also provided are methods of making power statistic measurements.

Abstract: A calibration system for calibrating a linearity corrector using the sum of filter products is proved, along with a method of calibrating the linearity corrector. The calibration system includes a first and second signal generator for introducing test signals into a signal processing system, such as an ADC. An acquisition memory and processor are provided for acquiring and analyzing the output of the signal processing system and then programming the filter coefficients into the linearity corrector. The method of calibration analyzes acquired intermodulation and harmonic components from the signal processing system and then finds the amplitude and phase response for the filters. The amplitude and phase response is then used to determine a set of filter coefficients.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes.

Abstract: An MOCVD process is provided for forming metal-containing films having the general formula M?xM?(1?x)MyOz, wherein M? is a metal selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, and Gd; M? is a metal selected from the group consisting of Mg, Ca, Sr, Ba, Pb, Zn, and Cd; M is a metal selected from the group consisting of Mn, Ce, V, Fe, Co, Nb, Ta, Cr, Mo, W, Zr, Hf and Ni; x has a value from 0 to 1; y has a value of 0, 1 or 2; and z has an integer value of 1 through 7. The MOCVD process uses precursors selected from alkoxide precursors, ?-diketonate precursors, and metal carbonyl precursors in combination to produce metal-containing films, including resistive memory materials.

Abstract: A process of lateral crystallization comprises providing a silicon film on a substrate surface, exposing a localized substrate region at the substrate surface to a laser heating source, and annealing a portion of the silicon film in thermal contact with the localized substrate region by exposing the silicon film to a low-fluence optical annealing source.

Abstract: A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; applying an electrical field treatment to the CMR thin film in the range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms); in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; and, in response to the applied bias voltage, creating an inductance between the top and bottom electrodes. When the applied bias voltage is varied, the inductance varies in response.

Abstract: Methods of forming an interfacial layer on a hydrogen-passivated substrate are provided. These methods utilize atomic layer deposition techniques incorporating metal nitrate-based precursors, such as hafnium nitrate or zirconium nitrate, without introducing a hydrating agent, or oxidizing agent, such as water, during the formation of the interfacial layer. Also provided are methods of forming high-k films, by first forming an interfacial layer on the surface of a hydrogen-passivated substrate, and then depositing one, or more, high-k dielectric films.

Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.

Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer.

Abstract: Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: A drain loaded 1T1R resistive memory device and 1T1R resistive memory array are provided. The resistive memory array comprises an array of drain loaded 1T1R resistive memory device structures. Word lines are connected across transistor gates, while a resistive elements are connected between transistor gates and bit lines. The resistive element comprises a material with a resistance that is changed electrically, for example using a sequence of electric pulses. The resistive element may comprise PCMO.

Abstract: An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators. A method is also provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

Abstract: An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere.

Abstract: A metal induced crystallization process is provided which employs an amorphous silicon film precursor deposited by physical vapor deposition, wherein the precursor film does not readily undergo crystallization by partial solid phase crystallization. Using this physical vapor deposition amorphous silicon precursor film, the amorphous silicon film is transformed to polysilicon by metal induced crystallization wherein the crystalline growth occurs fastest at regions that have been augmented with a metal catalyst and proceeds extremely slowly, practically zero, at regions which bear no metal catalyst. Accordingly, by use of the physical vapor deposition amorphous silicon precursor film in the process of the present invention, the metal induced crystallization process may take place at higher annealing temperatures and shorter annealing times without solid phase crystallization taking place.

Abstract: A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.