Abstract: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

Abstract: Methods of forming a SiGe layer overlying an insulator are provided. A layer of SiGe is deposited on a substrate and implanted with ion to form a defect region within the SiGe material below its surface. The SiGe layer is then patterned and transferred by contact bonding to an insulator on a second substrate. After contact bonding the structure is annealed to split the SiGe layer along the defect region. The splitting anneal will relax the SiGe layer. Additional annealing at higher temperatures may be used to further relax the SiGe layer. A layer of strained silicon may then be epitaxial deposited on the resulting structure of relaxed SiGe on insulator. Another method provides for epitaxially depositing a layer of silicon over the SiGe layer prior to patterning. The silicon layer would then be bonded to the insulator on the second substrate. The splitting anneal and additional anneals, if any, should then induce strain into the silicon layer.

Abstract: A pan/tilt camera system includes a sensor spaced from a rotational shaft of a pan/tilt camera, a detected piece rotated with the rotational shaft so as to correspond to the sensor, an origin setting unit rotating the rotational shaft in a first direction upon turn-on of a power and thereafter in a second direction opposite to the first direction so that the sensor detects a rear end of the detected piece for setting an origin, a pulse counter applying a predetermined number of pulses to the motor after set of the origin so that the rotational shaft is continuously rotated in the second direction and counting pulses applied to the motor until a front end of the detected piece with respect to the rotation direction of the detected piece is detected, and a backlash calculating unit comparing a count of the pulse counter with the predetermined number of pulses applied to the motor thereby to calculate an amount of backlash of the drive mechanism.

Abstract: A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.

Abstract: A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

Abstract: A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.

Abstract: A method of fabricating a variable resistance device, wherein the resistance is changed by passing a voltage of various pulse length through the device, includes preparing a silicon substrate; forming a silicon oxide layer on the substrate; depositing a first metal layer on the silicon oxide, wherein the metal of the first metal layer is taken from the group of metals consisting of platinum and iridium; depositing a perovskite metal oxide thin film on the first metal layer; depositing a second metal layer on the perovskite metal oxide, wherein the metal of the second metal layer is taken from the group of metals consisting of platinum and iridium; annealing the structure at a temperature of between about 400° C. to 700° C. for between about five minutes and three hours; and completing the variable resistance device.

Abstract: A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

Abstract: An array of crystalline silicon dies on a substrate and a method for yielding the array are provided. The method comprises: delineating an array of die areas on a crystalline semiconductor wafer; implanting the die areas with hydrogen ions; overlying the die areas with a layer of polymer to form, for each die, an aggregate including a die area first wafer layer; polymerically bonding an optically clear carrier to the die areas; thermally annealing the wafer to induce breakage in the wafer; forming, for each die, an aggregate wafer second layer with a thickness less than the die thickness; and, for each die, conformably attaching the aggregate wafer second layer to a substrate. The substrate can have an area of up to approximately two square meters and the wafer second layer can have a thickness of greater than and equal to approximately 20 nanometers.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties.

Abstract: A spin transistor employing the ferromagnetic semiconductor/semiconductor heterojunction is disclosed. The ferromagnetic semiconductor layers form heterojunctions directly on the source and drain of a regular field effect transistor. Using room temperature ferromagnetic semiconductor materials such as iron doped titanium oxide, the spin transistor can have improved spin injection efficiency due to the conductance matching of the ferromagnetic semiconductor with the semiconductor source and drain. The spin transistor further comprises writing plates to modify the magnetic polarization of the ferromagnetic layers to provide memory states. The spin transistor can be used as a memory cell in a magnetic random access memory with potentially large memory signal by utilizing the magnetic moment induced resistivity change.

Abstract: A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.

Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

Abstract: A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N+ region; implanting ions to form a shallow P+ region on the N+ region to form a P+/N junction; depositing a barrier metal layer on the P+ region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer, patterning and etching the top electrode layer, and completing the memory ar

Abstract: A system and method are provided for laser irradiating a semiconductor substrate using a multi-pattern mask. The method comprises: exposing a semiconductor substrate to laser light projected through a multi-pattern mask; advancing the mask and substrate in a first direction to sequentially expose adjacent areas of the substrate to each of the mask patterns in a first predetermined order; and, advancing the mask and substrate in a second direction, opposite the first direction, to sequentially expose adjacent areas of the substrate to each of the mask patterns in the first order. In one aspect, the method further comprises: forming a multi-pattern mask having a first plurality patterns aligned in the first order with respect to the first direction and a second plurality of patterns, corresponding to the first plurality of patterns, aligned in the first order with respect to the second direction.

Abstract: A multi-pattern shadow mask, shadow mask laser annealing system, and a multi-pattern shadow mask method for laser annealing are provided. The method comprises: supplying a silicon substrate; supplying a multi-pattern shadow mask with a plurality of aperture patterns; creating substrate alignment marks; with respect to the alignment marks, laser annealing a substrate region in a plurality of aperture patterns; forming a corresponding plurality of polysilicon regions; and, forming a corresponding plurality of transistor channel regions in the plurality of polysilicon regions. Typically, the shadow mask includes a plurality of sections, with each section having at least one aperture pattern. A shadow mask section can be selected to create a corresponding aperture pattern. If the mask section includes a plurality of aperture patterns, the selection of a section creates all the corresponding aperture patterns in the selected section.

Abstract: A method of CMP thin films during fabrication of IC devices includes preparing a substrate, including building IC component structures on the substrate; depositing a bottom electrode on the substrate; depositing a first CMP layer having a first known CMP selectivity on the substrate; patterning the first CMP layer to form a pattern having a lower margin; forming indicator structures on the first CMP layer in the pattern; depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer; CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and completing the IC structure.

Abstract: A method of chemical vapor deposition (CVD) of copper films includes preparing a substrate, including forming structures thereon have a barrier metal exposed surface; placing the prepared substrate into a CVD chamber; heating the substrate to a temperature of between about 200° C. and 250° C.; introducing a water flow in a carrier gas for at least one minute; stopping the water flow; and starting the flow of copper precursor.

Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.