Abstract: A method is provided to deposit niobium monoxide gates. An elemental metal target, or a composite niobium monoxide target is provided within a sputtering chamber. A substrate with gate dielectric, for example silicon dioxide or a high-k gate dielectric, is provided in the sputtering chamber. The sputtering power and oxygen partial pressure within the chamber is set to deposit a film comprising niobium monoxide, without excess amounts of elemental niobium, NbO2 insulator, or Nb2O5 insulator. The deposition method may be incorporated into a standard CMOS fabrication process, or a replacement gate CMOS process.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.

Abstract: A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.

Abstract: A memory device formed from selectively deposited PGO and a method for selectively forming a Pb5Ge3O11 (PGO) thin film memory device are provided. The method comprises: forming a silicon (Si) substrate; forming a silicon oxide film overlying the substrate; forming a patterned bottom electrode overlying the silicon oxide film; selectively depositing a PGO film overlying the bottom electrode; annealing; and, forming a top electrode overlying the PGO film. Selectively depositing a PGO film overlying the bottom electrodes includes: depositing a seed layer of PGO; and, forming a c-axis oriented PGO layer overlying the seed layer.

Abstract: A method is provided to produce thin film transistors (TFTs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. A gate is formed overlying the polycrystalline film. The polycrystalline film is doped to produce source and drain regions.

Abstract: A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.

Abstract: A 1:1 laser projection system and method are provided for laser irradiating a semiconductor film. The method comprises: exposing a mask to a beam of laser light; projecting laser light passed through the mask by a factor of one; exposing the area of a semiconductor film to the projected laser light having a first energy density; exposing an area of semiconductor film to a lamp light having a second energy density; and, summing the first and second energy densities to heat the area of film. When the semiconductor film is silicon, the film heating typically entails melting, and then, crystallizing the film. In some aspects of the method, the lamp is an excimer lamp having a wavelength of less than 550 nanometers (nm), and the laser is an excimer laser having a wavelength of less than 550 nm. In some aspects, the lamp is mounted to expose the bottom surface of the film including an area underlying the area being laser irradiated.

Abstract: A SiGe HBT BiCMOS on a SOI substrate includes a self-aligned base/emitter junction to optimize the speed of the HBT device. The disclosed SiGe BiCMOS/SOI device has a higher performance than a SiGe BiCMOS device on a bulk substrate. The disclosed device and method of fabricating the same also retains the high performance of a SiGe HBT and the low power, high-speed properties of a SOI CMOS. In addition, the disclosed method of fabricating a self-aligned base/emitter junction provides a HBT transistor having an improved frequency response.

Abstract: A common bit/common source line high density 1T1R (one transistor/one resistor) R-RAM array, and method for operating said array are provided. The R-RAM array comprises a first transistor with a drain connected to a non-shared bit line with a first memory transistor. The gates of the first, second, third, and fourth transistors are sequentially connected to a common word line. The R-RAM array comprises at least one common bit line. A second memory resistor is interposed between the drain of the second transistor and the common bit line. Likewise, a third memory resistor is interposed between the drain of the third transistor and the common bit line. A common source line connected to the sources of the third and fourth transistors. The R-RAM array comprises m rows of n sequential transistors.

Abstract: A method of forming a PGO thin film on a high-k dielectric includes preparing a silicon substrate, including forming a high-k gate oxide layer thereon; patterning the high-k gate oxide; annealing the substrate in a first annealing step; placing the substrate in a MOCVD chamber; depositing a PGO thin film by injecting a PGO precursor into the MOCVD chamber; and annealing the structure having a PGO thin film on a high-k gate oxide in a second annealing step.

Abstract: A method is provided for forming a relaxed single-crystal silicon germanium film on a silicon substrate. Also provided is a film structure with a relaxed layer of graded silicon germanium on a silicon substrate. The method comprises: providing a silicon (Si) substrate with a top surface; growing a graded layer of strained single-crystal Si1−xGex having a bottom surface overlying the Si substrate top surface and a top surface, where x increases with the Si1−xGex layer thickness in the range between 0.03 and 0.

Abstract: Accordingly, a method of suppressing energy spikes is provided comprising projecting a laser beam through a mask having a slit pattern comprising a corner region with edges, and a blocking feature with the corner region to reduce energy spikes projected on a substrate. An alternative method is provided, wherein the corner region is modified such that it is replaced by a more tapered shaped region, preferably a triangle. Also provided, are a variety of mask designs incorporating both corner regions, with and without one or more blocking features, and triangular regions, with or without one or more blocking features. The mask designs provide examples of mask modifications that may be used to reduce energy spikes.

Abstract: A method of physical vapor deposition includes selecting a target material; mixing at least two gases to form a sputtering gas mixture, wherein a first sputtering gas is helium and a second sputtering gas is taken from the gases consisting of neon, argon krypton, xenon and radon; forming a plasma in the sputtering gas mixture atmosphere to sputter atoms from the target material to the substrate thereby forming a layer of target material on the substrate; and annealing the substrate and the deposited layer thereon. An improved physical vapor deposition vacuum chamber includes a target held in a target holder, a substrate held in a substrate holder, a plasma arc generator, and heating rods. A sputtering gas feed system is provided for introducing a mixture of sputtering gases into the chamber; as is a vacuum mechanism comprising at least one turbomolecular pump for evacuating the chamber to a pressure of less than 16 mTorr during deposition.

Abstract: A TFT fabricated from a single crystal grain, and fabrication method has been provided. A large crystal grain is made by precise control of annealment, transition metal concentration, the density of transition metal nucleation sites, and the distance between nucleation sites. In one aspect of the invention, a diffusion layer permits the continual delivery of transition metal at a rate that both supports the lateral growth of di-silicide, and large distances between nucleation sites.

Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of strained SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 20%, by molecular weight; implanting H2+ ions into the SiGe layer; irradiating the substrate and SiGe layer, to relax the SiGe layer; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

Abstract: A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

Abstract: A method provides a fast motion search in advanced video signal coding systems based on a reference-frame prediction and a block-mode prediction so that a motion search of each block mode and each reference frame is not required. A reference frame prediction fp, spaced from the current frame by “p” number of frames, is determined by: p=min(n−1, p0+max(a,b,c,d)); wherein p0 is a pre-chosen positive integer, n is the total number of reference frames, wherein A, B, C, and D are image blocks adjacent to a searched block, and wherein the reference image blocks have been chosen from reference frames fa, fb, fc and fd. The search is conducted within frames f0 to fp, which is a subset of all the n reference frames, so that the total computational burden is significantly decreased with respect to prior art searches.

Abstract: A laser annealing mask is provided with cross-hatched sub-resolution aperture patterns. The mask comprises a first section with aperture patterns for transmitting approximately 100% of incident light, and at least one section with cross-hatched sub-resolution aperture patterns for diffracting incident light. In one aspect, a second mask section with cross-hatched sub-resolution aperture patterns has an area adjacent a vertical edge and a third mask section with cross-hatched sub-resolution aperture patterns adjacent the opposite vertical edge, with the first mask section being located between the second and third mask sections. The section with cross-hatched sub-resolution aperture patterns transmits approximately 40% to 70%, and preferably 50% to 60% of incident light energy density. In some aspects, the section with cross-hatched sub-resolution aperture patterns includes a plurality of different cross-hatched aperture patterns.

Abstract: A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables.

Abstract: A method of forming a PCMO thin film in a RRAM device includes preparing a substrate; depositing a metal barrier layer on the substrate; forming a bottom electrode on the barrier layer; spin-coating a layer of Pr1−xCaxMnO3 (PCMO) on the bottom electrode using a PCMO precursor; baking the PCMO thin film in one or more baking steps; annealing the PCMO thin film in a first annealing step after each spin-coating step; repeating the spin-coating step, the baking step and the first annealing step until the PCMO thin film has a desired thickness; annealing the PCMO thin film in a second annealing step, thereby producing a PCMO thin film having a crystalline structure of Pr1−xCaxMnO3, where 0.2<=X<=0.5; depositing a top electrode; patterning the top electrode; and completing the RRAM device.