Patents Represented by Attorney Mattingly, Stanger & Malur, P.C.
  • Patent number: 6893823
    Abstract: Different probes each having a specific base sequence are immobilized to each of independent areas formed on the surface of a substrate, complementary polynucleotides in a sample solution are hybridized to the probes, and each of the independent areas on the substrate is heated and then cooled in sequence, and hence the solution is recovered to extract different polynucleotides separately corresponding to individual probes.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: May 17, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Yasuda, Kazunori Okano, Hirokazu Kato
  • Patent number: 6893695
    Abstract: The waterproof/breathable moisture transfer liner for a snowboard boot includes an inner liner selected from technically advanced fabrics which are carefully selected. A series of layers are provided outside the inner liner including foam material layers, breathable membranes, a supportive mesh or a moldable foam, and an outer shell fabric. The applicability of the liner to alpine, cross country and hiking boots, along with appropriate variations for each application.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: May 17, 2005
    Assignee: Baychar Holdings, LLC
    Inventor: Dummy Baychar
  • Patent number: 6891182
    Abstract: In the automatic analyzer, the height of the test tubes is measured using the function of the optical information reader installed for discrimination of a sample. Various sensors installed so as to measure the height of the test tubes of the automatic analyzer can be omitted and decrease in cost, improvement of reliability, and improvement of maintenance capacity result.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 10, 2005
    Assignees: Hitachi, Ltd., Optoelectronics Co., Ltd.
    Inventors: Shigenori Watari, Haruo Matsuoka
  • Patent number: 6890761
    Abstract: In order to reduce carry-over of sample liquids in an automatic analyzer by a pipeting probe and resulting contamination of sample liquids by immersing the pipeting probe into sample liquids as shallow as possible, said pipeting probe is moving down to a position which is calculated and determined according to the detected height of a container temporarily stopping said probe there, and further moving down said probe to immerse said probe into the liquid in said container.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: May 10, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masato Ishizawa, Hideyuki Yanami
  • Patent number: 6889240
    Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
  • Patent number: 6888162
    Abstract: An electronic apparatus employs a polycrystalline semiconductor thin film structure formed of an insulating substrate and a plurality of polycrystalline layers laminated on the insulating substrate. A plurality of transistors are formed at the surface of the polycrystalline semiconductor thin film structure, each transistor being formed in a region of one of a plurality of crystal grains disseminated on the surface of the polycrystalline layers. A number of crystal grains in each of the polycrystalline layers is gradually reduced from a lower layer to an upper layer.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: May 3, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Yamaguchi, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii
  • Patent number: 6885722
    Abstract: A fuel assembly attains high burnup and increases reactor shut-down margin when loaded into a reactor core wherein a water gap width on a control rod side and a water gap width on a side opposite to the control rod side are almost equal to each other. The fuel assembly has a plurality of fuel rods arranged in a square lattice pattern, each fuel rod being filled with nuclear fuel pellets and also has at least one neutron moderator rod shifted toward one corner where a control rod is inserted, away from a cross sectional center of the fuel assembly.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: April 26, 2005
    Assignee: Hitachi, Ltd.
    Inventor: Ryoji Masumi
  • Patent number: 6883064
    Abstract: “Disk array system is presented wherein the plurality of disk array controlling units operate as the sole disk array controller so as to restrain the performance of the cache memory sections of the respective disk array controlling units from deteriorating owing to their physical packaging locations and to maximize the performance thereof in proportion to the number of the controlling units in use. Disk array controller is provided, which controller comprises a host switch interface section, the plurality of respective disk array controlling units provided with a channel interface section, a disc interface section and a cache memory section and a mutual connection network in connection with the channel interface sections, the disk interface sections and the cache memory sections of the respective disk array controlling units.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: April 19, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yoshida, Shuji Nakamura
  • Patent number: 6879571
    Abstract: In a mobile communication system using a code division multiple access (CDMA) method, spreading code detection and frame/slot timing synchronization (cell search) is conducted by using a long code masked symbol. The spreading factor of the long code masked symbol is set to a value lower than spreading factors of other ordinary symbols. As a result, it becomes possible to reduce the circuit scale and power dissipation of the mobile terminal and raise the speed of cell search.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: April 12, 2005
    Assignee: Hitachi, Ltd.
    Inventors: May Suzuki, Nobukazu Doi, Takashi Yano
  • Patent number: 6879575
    Abstract: In a mobile communication system using a code division multiple access (CDMA) method, spreading code detection and frame/slot timing synchronization (cell search) is conducted by using a long code masked symbol. The spreading factor of the long code masked symbol is set to a value lower than spreading factors of other ordinary symbols. As a result, it becomes possible to reduce the circuit scale and power dissipation of the mobile terminal and raise the speed of cell search.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: April 12, 2005
    Assignee: Hitachi, Ltd.
    Inventors: May Suzuki, Nobukazu Doi, Takashi Yano
  • Patent number: 6878586
    Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: April 12, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
  • Patent number: 6876023
    Abstract: A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: April 5, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Ishii, Kazuo Yano, Toshiyuki Mine
  • Patent number: 6874101
    Abstract: When receiving a write request from a processor, a control unit checks the condition of existence (or the presence/absence) in a cache for information necessary for generation of an updated value of a parity record, receives write data and reports the completion of the write request to the processor. In asynchronism with the write request from the processor, the control unit performs a load process for that information among the information necessary for generation of the updated value of the parity record which may be prepared in asynchronism with the write request from the processor and a write after process for the updated value of the parity record.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Hiroyuki Kitajima, Kouji Arai, Yoshihisa Kamo
  • Patent number: 6870854
    Abstract: Cells are discarded in conformity with the order of priority when congestion occurs by discarding cells of a traffic class without any special contract for a transfer rate at the time of setting up a connection. A node stores priority information concerning cell discard corresponding to a connection identifier and controls the cell discard in accordance with the discard condition determined by the accumulated number of cells for each connection in the node and cell priority.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: March 22, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Aimoto, Takeki Yazaki, Yoshihiko Sakata, Nobuhito Matsuyama
  • Patent number: 6870704
    Abstract: A low cost and highly reliable lubricating technique is realized by using a lubricant having an average molecular weight in the range of 900 to 2500. The lubricant is efficiently supplied to inner portions of a magnetic disk apparatus utilizing heat generated during operation of the apparatus. The method of assembling the apparatus is not affected since it is not necessary to provide a separate lubricant supply mechanism.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: March 22, 2005
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Mitsuhiro Shoda, Hiroshi Tani, Hiroyuki Matsumoto, Takayuki Nakakawaji
  • Patent number: 6867090
    Abstract: By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: March 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Hiratani, Shinichiro Kimura, Tomoyuki Hamada
  • Patent number: 6867502
    Abstract: A flip-chip BGA is disclosed which exhibits an excellent high-speed electric transmission characteristic while minimizing the formation of voids in sealing resin filled between a semiconductor chip and a wiring substrate. A silicon chip is flip-chip-mounted on a package substrate, and in a central area of a main surface of the silicon chip are arranged a power supply circuit, an input/output circuit, and plural bonding pads, while in the other area than the central area are arranged solder bumps in a matrix form, the solder bumps being electrically connected to the bonding pads through Cu wiring. Of the solder bumps, solder bumps for input/output power supply and solder bumps for the input and output of a data signal are arranged in a first area adjacent to the central area, and solder bumps for address signal input are arranged in a second area located outside the first area.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Mitsuaki Katagiri, Masami Usami, Kenji Ujiie
  • Patent number: 6867446
    Abstract: In a semiconductor memory device having a capacitor layer comprising a dielectric film or a ferroelectric film, as an interlayer insulation film formed between the capacitor and a wiring layer formed at the upper part thereof or an insulation film which covers the wiring layer, a multilayered film is used which consists of a first insulation film and a second insulation film laid upon the other; the former being a lower layer and being formed of an organic film, and the latter being an upper layer and being formed of a hard-mask material. This makes it possible to prevent thin film comprised of a dielectric material or a ferroelectric material from any deterioration caused by the hydrogen and water contained in the interlayer insulation film and passivation film of the semiconductor memory device and also by the stress of these films.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Miharu Otani, Jun Tanaka, Kazufumi Suenaga, Kiyoshi Ogata
  • Patent number: 6868415
    Abstract: On an information registering equipment, content of interest rendered by media, such as a video image of interest distributed by TV broadcasting is captured and displayed. Position/area on the image are defined with a mouse or the like to obtain the target position/area. Information to identify the content is obtained from the TV tuner. Reference information is obtained by inputting through input means or by retrieval from the server for reference information. The thus obtained information specifics are transmitted to an information search equipment that in turn stores then into its database. An information viewing equipment obtains the target position/area and information to identify the content of interest and transmits the thus obtained data to the information search equipment. The information search equipment matches that data with each data record in the database and transmits reference information to the information viewing equipment on which the reference information is displayed.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: March 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kageyama, Tomokazu Murakami, Hisao Tanabe
  • Patent number: 6864134
    Abstract: This invention provides a manufacturing method for fabricating on the same substrate both high voltage thin film transistors suitable for driving liquid crystal and low voltage drive high performance thin film transistors. In addition, this invention provides a thin film transistor substrate where the area occupied by a storage capacitor in each pixel is reduced to raise the aperture ratio of the display unit. One aspect of this invention provides a manufacturing method characterized in that the impurity regions of both high voltage thin film transistors and high performance thin film transistors which differ in the thickness of gate insulation are formed by implanting a dopant through the same two-layered film. Another aspect of this invention reduces the area occupied by the drive circuit in the display unit by utilizing an extension of one layer of the insulation film included in each thin film transistor.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: March 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Satou, Toshihiko Itoga, Takeo Shiba