Patents Represented by Attorney Mattingly, Stanger & Malur, P.C.
  • Patent number: 6838825
    Abstract: A plasma display includes a display panel and a driving circuit for driving the display panel. A space for at least one color, of spaces between barrier ribs for defining discharge spaces for red, green and blue colors of the display panel is different from the spaces for other colors.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Shiiki, Choichiro Okazaki, Teruki Suzuki, Keizo Suzuki, Tadashi Furukawa, Masaji Ishigaki
  • Patent number: 6836830
    Abstract: In a computer system having a computer, a storage system having storage units being coupled to the computer and for storing user data used by the computer, and a backup device being coupled to the computer and the storage system, a backup method is presented for obtaining a backup of the data stored in the storage unit to the backup device. The storage system holds the user data dually in a first and a second storage units. In backing up the user data, a split instruction for releasing the duplex state of the first and the second storage units is sent from the computer to the storage unit. In response to the split instruction, the storage system interrupts the reflection of the update of the user data to the first storage unit onto the second storage unit. Then, a copy instruction for copying the user data held in the second storage unit to the backup device is sent from the computer to the storage system.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: December 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Yamagami, Minoru Kosuge, Hiroshi Arakawa, Takashi Oeda, Koichi Kimura, Haruaki Watanabe, Kenzo Tabata
  • Patent number: 6834572
    Abstract: A woodworking machine includes an adjustable table for holding a workpiece thereon and a drive chain saw spaced from the table and having cutting teeth on one edge and drive engaging chain guides adjacent an opposite edge. The drive engaging chain guides engage a drive wheel driven by a motor. A support plate is positioned above the table and has a plurality of slots therein for adjustably mounting a plurality of roller guide elements positioned to engage both sides of the drive chain saw. Each of the roller guide elements includes at least one groove in an outer periphery thereof and the drive chain saw includes circular chain guides which mate with the groove. Threaded pins are provided for adjusting the position of each of the roller guide elements to engage the drive chain saw whereby a portion of the drive chain saw is formed into an undulating shape to cut curved surfaces in the workpiece when the drive chain saw and the workpiece come into contact.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: December 28, 2004
    Inventor: Paul A. Richmond
  • Patent number: 6836479
    Abstract: An input interface segments a variable length packet into plurality of fixed length cells and generates an internal switching information based on the header information of the variable length packet. The input interface transmits the information to a switch and, after that, transmits the cells as the following cells of the information to the switch. The switch performs switching processing to the succeeding cells based on the information. Therefore, the information is not added to the cells. When an input interface starts to transmit cells generated from a packet to its destination output interface through the switch, the switch is reserved until all the cells arrive at the output interfaces.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: December 28, 2004
    Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.
    Inventors: Kenichi Sakamoto, Nobuhito Matsuyama, Takeshi Aimoto, Noboru Endo, Koji Wakayama, Norihiko Moriwaki
  • Patent number: 6833618
    Abstract: The invention provides a memory system that allows connection of a memory controller to each of plural memory modules in an equal distance. The memory system includes a memory controller, three memory modules, a single socket which the three memory modules can be inserted into and pulled out from, and a mother board on which the memory controller and the socket are mounted, etc. And, the memory controller and each of the memory modules are connected in an equal distance through the socket pins of the socket that are branched from bus wirings on the mother board. The socket is furnished with three sets of the plural socket pins in a radial form, in correspondence with each of the memory modules. The socket has two types of structures: one has three module-board contacts for one board-bus connection, and the other has one module-board contact for one board-bus connection.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: December 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takao Ono, Hironori Iwasaki, Mitsuya Tanaka
  • Patent number: 6833577
    Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: December 21, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Yuichi Matsui, Masahiko Hiratani
  • Patent number: 6832175
    Abstract: A hydraulic excavator 1 working in fields includes a controller 2 for measuring a working time for each of an engine 32, a front 15, a swing body 13, and a travel body 12, storing measured data in a memory of the controller 2, and then transferring it to a base station computer 3 via satellite communication, an FD, etc. The transferred data is stored as a database 100 in the base station computer 3. The base station computer 3 reads the data stored in the database 100 for each hydraulic excavator, calculates a working time of a part belonging to each section on the basis of the working time of that section, and compares the calculated working time with a preset target replacement time interval of the relevant part, thereby calculating a remaining time up to next replacement of the relevant part and managing the scheduled replacement timing thereof.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: December 14, 2004
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Hiroyuki Adachi, Toichi Hirata, Genroku Sugiyama, Hiroshi Watanabe, Shuichi Miura, Koji Mitsuya, Yoshiaki Saito, Atsushi Sato
  • Patent number: 6831294
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: December 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 6832227
    Abstract: Database optimizing method and system are provided to optimally locate data. Only data satisfying conditions desired by a user is extracted among an access log. Values of a part of the data are translated on the basis of a translation table, and aggregated on the basis of aggregation condition rules. The obtained aggregation result is presented to the user. In addition, data in the database are optimally relocated on the basis of the obtained aggregation result.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: December 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yumiko Seki, Masami Kameda, Takeshi Fujii, Yoshifumi Yamashita
  • Patent number: 6831360
    Abstract: A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: December 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Yamaura, Hirokazu Nakajima, Nobuyoshi Maejima, Mikio Negishi, Tomio Yamada, Tomomichi Koizumi, Tsuneo Endoh
  • Patent number: 6830837
    Abstract: It is an object of the present invention to provide a high reliability magnetic storage apparatus capable of performing writing and reading back of high density information. The magnetic storage apparatus is so configured as to have a longitudinal magnetic recording medium including: a magnetic layer formed on a non-magnetic substrate via a plurality of underlayers; the magnetic layer including a lower magnetic layer containing Ru in an amount of not less than 3 at % to not more than 30 at %, and Cr in an amount of not less than 0 at % to not more than 18 at %, and further containing at least one of B or C in an amount of not less than 0 at % to not more than 20 at %, and an upper magnetic layer containing Co as a main component disposed thereon via a non-magnetic intermediate layer.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: December 14, 2004
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Tetsuya Kanbe, Hiroyuki Suzuki, Yotsuo Yahisa, Yoshiyuki Hirayama, Hidekazu Kashiwase
  • Patent number: 6831244
    Abstract: A gas-insulated switch equipped with a fixed contact and a moving contact that can contact with and separate from the fixed contact, wherein a single shock absorber absorbs the shock in both the breaking action and the closing action of the moving contact.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: December 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Kawamoto, Kenichi Okubo, Tetsu Ishiguro
  • Patent number: 6829574
    Abstract: Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: December 7, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Ito, Akira Yamagiwa, Nobuaki Ejima, Ryoichi Kurihara, Masakazu Sakaue, Yasuhiro Uemura
  • Patent number: 6829031
    Abstract: For obtaining both high brightness under condition of small-sized and simplified structure and suppression of increase in temperature of liquid crystal display elements and polarizing elements, in a liquid crystal display apparatus, comprising: a liquid crystal display element 2 for converting light from a light source into display picture depending on a driving signal; an optical projection system 1b containing a first optical element 1a and for projecting said light signal toward an object of projection; exit side polarizing elements 3b; a holding member 6 for holding them with the liquid crystal display element 2; and cooling medium 5; incident side polarizing elements 3a, wherein, a space is defined by either one of the incident side polarizing elements 3a and the liquid crystal display element 2, the first optical element 1a, between the liquid crystal display element 2 and the first optical element 1a, and the holding member 6, and said space is filled up with the cooling medium 5.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: December 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Toru Numata, Yasuo Otsuka, Mikio Shiraishi, Koji Hirata, Naoyuki Ogura, Shigeru Inaoka, Kazunari Nakagawa, Shigeru Mori, Masahiko Yatsu
  • Patent number: 6829232
    Abstract: A server 3b for controlling a gateway 2 connecting a transport layer and an IP network has the function of accessing a service control point (SCP) 4 via a service control gateway 1a. A server 3 for controlling terminals on the IP network stores information of correspondence between telephone number of a terminal and the IP address. When a signal including number information which requires an access to the SCP is received from a terminal 11 managed by the server 3a, an interrogation request is multicasted to the other servers each having the function of accessing the SCP. A server which has sent a response signal accesses the SCP via the service control gateway to provide an IN service process.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: December 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yukiko Takeda, Tetsuro Yoshimoto, Satoshi Shimizu, Shiro Tanabe
  • Patent number: 6829186
    Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: December 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Kanno, Kiyoo Itoh
  • Patent number: 6829749
    Abstract: The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit diagram editor 1902 arranges a coupler symbol 100 stored in a component symbol storage section 1904 when the coupler is arranged in preparing a circuit diagram. A layout section 1935 of a layout diagram editor 1922 layouts two wirings constituting the coupler by use of circuit diagram information and coupler information in which a coupler length and a coupler interval are defined. An object extraction section 1937 of a wiring check section 1936 extracts components and wirings from the layout diagram, and passes these to a wiring checker 1938. At this time, the coupler is passed to the wiring checker as one component that cannot be decomposed no more. Therefore, an interval between two wirings constituting the coupler is not checked.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: December 7, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Osaka, Toyohiko Komatsu
  • Patent number: 6828174
    Abstract: With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: December 7, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Mitsuaki Katagiri, Yuji Shirai, Yoshiyuki Kado
  • Patent number: 6826212
    Abstract: A module for optical communication intended for decreasing the consumption power of a modulator integrated laser, in which a, multiple-quantum well constituting a laser active layer region comprises InGaAlAs/InGaNAs to keep the reliability and optical power level even when a chip is kept at a high temperature, and the difference of wavelength between the oscillation wavelength and the band gap wavelength of the modulator and the laser should be made greater in proportion with the elevation of the chip setting temperature for maintaining the transmission performance, by which the temperature difference between the module case temperature and the chip setting temperature is reduced to decrease the module consumption power.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: November 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masataka Shirai, Junichiro Shimizu, Shinji Tsuji
  • Patent number: 6824273
    Abstract: A liquid crystal projector comprises an illuminating optical system including a light source, a color separating optical system for separating illuminating light rays emitted by the illuminating optical system into light rays of three colors, a projection lens unit comprising a projection lens, a cross dichroic prism disposed near a light receiving end of the projection lens, and a plurality of liquid crystal panels arranged around the cross dichroic prism, and a light source power supply for supplying power to the light source. The projection lens unit, the color separating optical system, the illuminating optical system and the light source power supply are arranged in that order. The liquid crystal projector has an outside size in a horizontal plane of 263 mm by 318 mm or below. The liquid crystal panels have a display screen size of 0.9 in. A cooling fan for cooling the plurality of liquid crystal panels is disposed beside the projection lens.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: November 30, 2004
    Assignees: Hitachi, Ltd., Hitachi Video Information System, Inc.
    Inventors: Nobuhiko Konuma, Hidetomo Yoshimura, Seiichi Sekiguchi, Mikiharu Kuwata, Masaharu Deguchi, Takashi Kakuda, Yutaka Matsuda, Takuya Shiaki, Futoshi Yamasaki, Atsushi Ishibashi, Koichi Umezawa, Takeshi Hoshino, Shigehisa Hagura, Makoto Fukatsu, Nobuyuki Kaku, Kenji Fuse, Satoshi Ohuchi, Tomohiro Miyoshi, Naohiro Ozawa, Masahiko Yatsu, Yasuo Otsuka, Takesuke Maruyama