Patents Represented by Attorney Mattingly, Stanger & Malur, P.C.
  • Patent number: 6845497
    Abstract: Patterns for exposure are divided into subdivided regions taking into consideration a scope of an effect of backscattering, the Coulomb effect, and process factors, respectively, on errors in dimensions, and a pattern area occupancy ratio (pattern area density) within the respective subdivided regions is retained, thereby executing exposure with patterns after finding dimensions of pattern modification as the function of the respective pattern area densities. As a result, it becomes possible to fabricate a mask provided with correction for the errors in the dimensions, caused by plural factors such as backscattering, the Coulomb effect, and process factors, and to obtain highly accurate patterns for exposure. Further, use of pattern area density maps enables data processing time necessary for correction to be considerably reduced.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: January 18, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Murai, Hiroshi Fukuda
  • Patent number: 6842637
    Abstract: A magnetic field measurement apparatus includes a plurality of magnetometers each having SQUID's and three detection coils, one of which detects each of three orthogonal directional magnetic field components (Bx, By, Bz) of a magnetic field generated from a subject to be inspected, a display which displays time variation of waveforms of the magnitude (?(Bx2+By2+Bz2)) of magnetic field synthesized by square sum of each of the three orthogonal directional magnetic field components of the magnetic field generated from the subject to be inspected, a holder for holding a Dewar's vessel for arranging magnetometers therein, and a controller for controlling a positional relationship between the subject to be inspected and the Dewar's vessel.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Tsukada, Akihiko Kandori, Tsuyoshi Miyashita, Hiroyuki Suzuki, Hitoshi Sasabuchi
  • Patent number: 6842309
    Abstract: A magnetic head slider, for sliding on a magnetic disk, which comprises a leading edge, a trailing edge, an air bearing surface having a front step bearing of submicron depth made from the leading edge, and a rail surface made from the front step bearing. A negative pressure recess, which is more profound than the front step bearing, is made from the rail surface, and a side step bearing with a depth identical to that of the front step bearing is made from the rail surface, wherein the ratio of depth R of the recess and depth ?s of the front step bearing is R/?s?5.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hidekazu Kohira, Masaaki Matsumoto, Kiyoshi Hashimoto, Masayoshi Endo, Akio Takakura, Yoshihori Takeuohi, Shinsuke Higuchi, Akira Iida
  • Patent number: 6841881
    Abstract: With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Mitsuaki Katagiri, Yuji Shirai, Yoshiyuki Kado
  • Patent number: 6841871
    Abstract: Concerning a plurality of second bonding pads that are electrically connected with a plurality of first bonding pads provided on an IC chip and having a predetermined narrow pitch, a technique is disclosed that allows the plurality of second pads to be provided on the IC chip. This makes it possible to provide the second pads at desired positions. Accordingly, it becomes possible to form, by printing with a low accuracy, respective interconnections that connect the plurality of second pads with a plurality of electrodes provided on a substrate. Also, matching of positions is executed between the plurality of second pads and the plurality of electrodes formed on the substrate by printing. This matching makes it possible to electrically connect the second pads with the electrodes provided on the substrate in a such a manner that they are opposed to each other.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6842415
    Abstract: A method for recording information is disclosed in which an information recording medium is irradiated with a recording energy beam power-modulated into at least a record power level and a record-ready power level lower than the record power level. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion. Also, only in the case where the energy beam is modulated by the power lower in power level than the record-ready power level after the last pulse of the energy beam pulse train including at least one pulse for forming a mark portion and the mark portion is followed by a space portion of a predetermined length, the particular radiation energy of low power level is reduced as compared with when the mark portion is followed by a space potion of a different length.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miyamoto, Tsuyoshi Toda, Masatoshi Ohtake, Motoyasu Terao, Junko Ushiyama, Keikichi Andoo, Yumiko Anzai, Akemi Hirotsune, Tetsuya Nishida, Hideki Saga
  • Patent number: 6841946
    Abstract: An object of the present invention is to obtain excellent images which are free from distortion in a flat display apparatus including electron-emitter elements, phosphors, and spacers. A structure of the present invention is such that the display apparatus comprises a display panel including a first substrate having a plurality of electron-emitter elements, a second substrate having phosphors, and spacers; and driving means employing a line-sequential scanning method; wherein scan pulse output is performed by the driving means, and the driving means performs scanning in such a manner that a scan is performed in the direction of approaching a relevant one of the spacers from far. Thus, the present invention realizes the excellent display images which are free from distortion by largely reducing or eliminating influence of charging of the spacers to be exerted on the images.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Mutsumi Suzuki, Masakazu Sagawa, Toshiaki Kusunoki
  • Patent number: 6842118
    Abstract: An overload detection device for a high-lift work vehicle is capable of detecting the load on the work platform. A base 10 of the work platform is supported with a bracket 9 at, at least, three supporting portions. Load sensors 11 each constituted of a plate member 14 and distortion gauges 15˜18 detect the extent of flexure of at least two of the supporting portions.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: January 11, 2005
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Teruo Igarashi, Atsushi Tadokoro
  • Patent number: 6842875
    Abstract: A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masaharu Kondo, Seiichi Mita
  • Patent number: 6842540
    Abstract: A surveillance image is acquired from a surveillance camera. Supplement information (such as date and time, and surveillance camera number) relating to the surveillance image is acquired. By imaging the supplement information, supplement information image data is generated. A quantized discrete cosine transform coefficient block obtained by conducting discrete cosine transform and then quantization on surveillance image data of the surveillance image is added to a quantized discrete cosine transform coefficient block obtained by conducting discrete cosine transform and then quantization on the supplement information image data. A resultant sum is subjected to Huffman encoding. The result is recorded.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masataka Okayama, Harumi Morino, Takeo Tomokane, Kenji Watanabe, Koichi Inoue, Tomohisa Kohiyama, Akio Hayashi
  • Patent number: 6838631
    Abstract: A power use circuit breaker includes an arc generating switching unit which adds an electrical resistance in a circuit during current interruption to attenuate a current to be interrupted, a vacuum bulb which is electrically connected in series with the arc generating switching unit and interrupts the attenuated current and a current conducting switching unit connected in parallel with the series circuit of the vacuum bulb and the arc generating switching unit. For current conduction the current conducting switching unit is closed after the vacuum bulb and the arc generating switching unit are closed, and for current interruption after opening the current conducting switching unit, the vacuum bulb and the arc generating switching unit are opened.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: January 4, 2005
    Assignees: Hitachi, Ltd., Hitachi Electric Systems Co., Ltd.
    Inventors: Noriaki Munakata, Yukio Kurosawa, Haruo Honda, Shigetoshi Oouchi, Masaki Shinohara
  • Patent number: 6838682
    Abstract: There is provided an electron beam exposure technique which permits optical adjustment in an electron optics system using a doublet lens necessary for large field projection. Electron beam exposure equipment having a part forming one image by at least two electromagnetic lenses, has means measuring the position of an electron beam near an image plane with changing excitation of at least two lenses at the same time; and control means feeding back the measured result to aligners or the intensity of the lenses.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: January 4, 2005
    Assignees: Hitachi High-Technologies Corporation, Canon Kabushiki Kaisha
    Inventors: Yasunari Sohda, Osamu Kamimura, Hiroya Ohta, Susumu Gotoh
  • Patent number: 6839083
    Abstract: A monitoring device for security in automatic teller machine, wherein a security monitoring unit and a security data recording unit are robust in structure so that they are not easily destructed. Even if the automatic teller machine itself is stolen and a commercial power source is shut down, the security monitoring unit and the security data recording unit can be operated with a backup power supply unit to wirelessly transmit security information, thereby making it possible to keep track of where the automatic teller machine is located.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Hamamoto, Noriaki Kawamoto
  • Patent number: 6838767
    Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: January 4, 2005
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Tsugihiko Hirano, Hidemi Ozawa
  • Patent number: 6838771
    Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: January 4, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
  • Patent number: 6838667
    Abstract: By use of charged particle beam images picked up in different conditions, a positional displacement caused by parallax is analyzed, and an optics of an apparatus for charged particle beam microscopy is corrected automatically. An analysis method using phase difference of Fourier transform images and having analytic accuracy lower than that for one pixel is adopted for the displacement analysis. In addition, a degree of coincidence between images calculated in this analysis method is used as a criterion for evaluating the reliability of an analysis result. Since the analysis method based on parallax is low in specimen dependency, the operation range is expanded. In addition, by adopting a high-accuracy displacement analysis method, the apparatus correction accuracy is improved by one digit. A malfunction preventing flow is added using the degree of coincidence as a judgement criterion. Thus, the apparatus can deal with unmanned operation.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Ruriko Tsuneta, Masanari Koguchi, Mari Nozoe, Muneyuki Fukuda, Mitsugu Sato
  • Patent number: 6839847
    Abstract: An IC card having a storage memory including a program storage unit for storing a program and a data storage unit for storing data and a central processing unit for executing a predetermined process in accordance with the program to process the data, the program including one or more data process units each having a process instruction for giving an execution instruction to the central processing unit, wherein a data process order is randomly exchanged and a dummy process is added to thereby reduce the dependency of consumption current of an IC chip upon the data process.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masaru Ohki, Yasuko Fukuzawa, Susumu Okuhara, Masahiro Kaminaga
  • Patent number: 6839134
    Abstract: At the time of analytical measurement of a sample by the fluorescence measuring device or the phosphorescence measuring device, both the optical path of exciting light emitted from the light source to the sample and the optical path of fluorescence or phosphorescence emitted from the sample to the detection unit are shut off. Both are shut off by one chopper.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Michihiro Saito, Satoshi Takahashi, Koichi Matsumoto
  • Patent number: 6838315
    Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a substrate in which a plurality of electrode members are individually placed on one main surface thereof in separated form, a step of placing a semiconductor chip on the one main surface of the substrate and electrically connecting a plurality of electrodes formed on one main surface of the semiconductor chip and the plurality of electrode members respectively, a step of forming a resin encapsulater for sealing the semiconductor chip and the plurality of electrode members on the one main surface of the substrate, and a step of separating the semiconductor chip and the plurality of electrode members from the substrate together with the resin encapsulater.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: January 4, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Tadatoshi Danno, Katsuo Arai, Ichio Shimizu
  • Patent number: 6839200
    Abstract: In a composite magnetic head comprising a magnetoresistive read head including a magnetic thin film having a magnetoresistive effect and soft magnetic members interposing the soft magnetic film between them through a non-magnetic insulation layer, an induction type write head including poles formed in a moving direction of a medium and a conductor crossing the poles, and disposed in the proximity of the magnetoresistive head, and a substrate supporting these heads, the present invention discloses a composite magnetic head characterized in that part of a floating surface inclusive of the magnetic head constituent members has recesses and the read/write operations to and from the medium are effected by the portion interposed by these recesses.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hisashi Takano, Naoki Koyama, Hideo Tanabe, Eijin Moriwaki, Isamu Yuito, Kazuo Shiiki, Tsuyoshi Ohnishi, Tohru Ishitani, Toshio Kobayashi, Hideo Todokoro, Chiaki Ishikawa