Patents Represented by Attorney Mattingly, Stanger & Malur, P.C.
  • Patent number: 6861703
    Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: March 1, 2005
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 6861294
    Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shigeharu Tsunoda, Junichi Saeki, Isamu Yoshida, Kazuya Ooji, Michiharu Honda, Makoto Kitano, Nae Yoneda, Shuji Eguchi, Kunihiko Nishi, Ichiro Anjoh, Kenichi Otsuka
  • Patent number: 6861905
    Abstract: A power amplifier system has a high frequency power amplifier circuit section employing source-grounded enhancement type n-channel MESFETs for receiving a drain bias voltage and a gate bias voltage of zero volts or positive low potentials supplied from a unipolar power supply, and amplifying a superposed input signal therewith to output an amplified signal indicative of a change in drain currents. An output matching circuit section applies impedance matching to the amplified signal and outputs the resultant signal. A gate bias voltage circuit section supplies a gate bias voltage to the high frequency power amplifier circuit. When a forward direct current gate voltage is applied to a gate terminal with a source terminal coupled to ground, the DC gate voltage becomes greater than or equal to 0.65 volts, the DC gate voltage causing a gate current value per gate width of 100 micrometers to exceed 100 microamperes.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: March 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Atsushi Kurokawa, Masao Yamane
  • Patent number: 6862232
    Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Hanzawa, Takeshi Sakata
  • Patent number: 6861742
    Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: March 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Miyamoto, Ichiro Anjo, Asao Nishimura, Mitsuaki Katagiri, Yuji Shirai, Yoshihide Yamaguchi
  • Patent number: 6860662
    Abstract: When a sheet feeding/processing control part judges that when a sheet feed request of feeding a sheet by a sheet feed amount is present, an actual cutting position passes a cutter, it divides the requested sheet feed amount into first and second sheet feed amounts. To start, a sheet is fed by the first sheet feed amount, so that an actual cutting position just reaches the cutter. In a state that the sheet stops, a cutter motor is driven to operate the cutter and to cut the sheet at the cutting position. After the sheet is cut, a sheet feed motor is driven to feed the sheet by the second sheet feed amount. Also in feeding the sheet by the second sheet feed amount, a similar process is executed.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: March 1, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Katsutoshi Iwamura
  • Patent number: 6862505
    Abstract: A vehicle-mounted information processing apparatus such as a car-navigation system detects that a key switch of the vehicle has been set up at a Lock position (i.e., the engine is stopped). After that, the apparatus performs data reproduction of data files in an order from the oldest, then re-recording the reproduced data files with no change added thereto. Here, the above-described data files, which are stored within a magnetic disk device built in the apparatus, have been not updated for a constant time-period. This re-recording prevents a data loss caused by a thermal decay in the case where the magnetic disk device is mounted inside the vehicle that is likely to have existed under a high-temperature environment for a long time-period.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: March 1, 2005
    Assignees: Hitachi, Ltd., Xanavi Informatics Corporation
    Inventors: Naoki Satoh, Takashi Yamaguchi, Atsushi Saito, Kozo Nakamura, Mikio Tokuyama, Shigeo Nakamura, Hiroyuki Kohida, Hirohisa Miyazawa
  • Patent number: 6857562
    Abstract: An electronic money system of a token and value mixed type includes an electronic money card of a type in which a token type for preferentially paying the coin money and paying the bill money when a coin money balance is insufficient for payment, and for recording issuance numbers of bills paid/received in a transaction history in a memory area of the electronic money card. An automatic transaction machine (ATM) reads, from an electronic money card, issuance number of bills for deposit and an issuance number of an invalid bill, and transmits the numbers to a computer of a bank.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: February 22, 2005
    Assignee: Hitachi, Ltd.
    Inventor: Shigeru Sasaki
  • Patent number: 6855483
    Abstract: A negative pattern is formed to be transparent in the far ultraviolet region including the wavelength 193 nm of an ArF excimer laser and, despite its chemical structure having high dry etching, does not swell and has excellent resolution. An acid-catalyzed reaction is utilized wherein a ?-hydroxy or ?-hydroxy carboxylic acid structure is partially or entirely converted to a ?-lactone or ?-lactone structure. The negative pattern is developed with an aqueous alkali solution without swelling.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: February 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hattori, Yuko Tsuchiya, Hiroshi Shiraishi
  • Patent number: 6856574
    Abstract: A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (111, 113 and 115) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (112, 114 and 116) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: February 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Iwahashi, Keiichi Higeta
  • Patent number: 6856962
    Abstract: A schedule management system includes a schedule data table which stores the schedule data including an identifier of a schedule owner, the time zone, activity and the state of the schedule. A definition data table stores the definition data for determining the relation between the registration and display of the schedule and the schedule and the state in he schedule data. A schedule data registration unit accepts a schedule reservation request, determines whether the schedule registration is permitted or not based on the schedule state of the schedule data existing in the schedule data table and the definition data, and when the schedule registration is permitted, registers the reservation schedule in the schedule data table. A schedule data approval unit accepts a request from the schedule owner for approving/disapproving the schedule and rewrites the schedule state of the corresponding schedule data in the schedule data table.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: February 15, 2005
    Assignee: Hitachi, Ltd.
    Inventor: Tetuya Yonemitsu
  • Patent number: 6855903
    Abstract: A vacuum switch comprises a vacuum container, a grounding switch and a load switch disposed in the container, and an external connection conductor disposed in the vacuum container and to be connected electrically inside and outside the vacuum container, and it is characterized in that the grounding switch and the external connection conductor are electrically connected to each other in the vacuum container.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: February 15, 2005
    Assignees: Hitachi, Ltd., The Tokyo Electric Power Company, Incorporated
    Inventors: Shuuichi Kikukawa, Yasuaki Suzuki, Tooru Tanimizu, Koichi Murata, Ryotaro Hanabuchi
  • Patent number: 6855035
    Abstract: The apparatus and method for producing a substrate having a substrate surface by polishing the substrate surface, which includes a metallic wire. A polishing liquid is supplied a clearance between the substrate surface and the surface of a polishing pad. The polishing liquid includes an acid which dissolves the oxidized part of the substrate surface and is substantially free of solid abrasive powder. A relative movement is generated between the substrate surface and the polishing pad surface while the substrate surface is pressed against the polishing pad surface while the polishing liquid is supplied so that the dissolved oxidized part of the substrate surface can be removed from the substrate.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshio Homma, Noriyuki Sakuma, Naofumi Ohashi, Toshinori Imai
  • Patent number: 6854259
    Abstract: Disclosed is a gas turbine power generating system capable of achieving a high output power and a high power generating efficiency under conditions with a small amount of supplied water and less change in design of a gas turbine. A fine water droplet spraying apparatus (11) is disposed in a suction air chamber (22) on the upstream side of an air compressor (2), and a moisture adding apparatus (7) for adding moisture to high pressure air supplied from the compressor (2) is disposed. A regenerator (5) for heating the air to which moisture has been added by using gas turbine exhaust gas as a heat source is also provided. With this configuration, there can be obtain an effect of reducing a power for the compressor (2) and an effect of increasing the output power due to addition of moisture to air (20) for combustion. Further, since the used amount of fuel is reduced by adopting a regenerating cycle, the power generating efficiency is improved.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: February 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Hatamiya, Masahiko Yamagishi, Osamu Yokomizo, Yoshiki Noguchi, Moriaki Tsukamoto
  • Patent number: 6854126
    Abstract: In an information recording medium, a first protective layer, a recording film, a second protective layer and a reflective layer are provided on a substrate sequentially from a side where light is irradiated, the first protective layer having a film thickness of 2 nm to 25 nm. 95 atomic % or more of a material of the first protective layer is SiO2—In2O3—SnO2—ZnS, and a ZnS amount in the first protective layer is in the range of 4 mol % to 33 mol %.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: February 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Akemi Hirotsune, Motoyasu Terao, Yumiko Anzai
  • Patent number: 6853217
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: February 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Patent number: 6854034
    Abstract: A computer system which has a plurality of computers and a storage device subsystem connected to the plurality of computers. The storage device subsystem has a plurality of storage devices and a plurality of interfaces, through which the subsystem is connected to the computers. One of the plurality of computers has a management means for holding therein data indicative of the storage devices and a connection relationship between the computers and storage device subsystem. Each computer, when wanting a new device, informs the management means of its capacity and type. The management means receives its notification and selects one of the storage devices which satisfies the request. And the management means instructs the storage device subsystem to set predetermined data in such a manner that the computer can access the selected device.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: February 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Kitamura, Kenji Yamagami, Tatsuya Murakami
  • Patent number: 6852553
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Patent number: 6852992
    Abstract: Light having polarization is irradiated onto an article, and then quality of the article is diagnosed using a pre-input correlation function between quality of the article and a variation of polarization of the light reflected from the article. Further, the quality of the article is diagnosed by measuring a reflection absorbance difference or a reflection absorbance ration of light from the article between two wavelenghts, and by measuring a depolarization degree of polarized light of the reflected light from the surface of the article. The quality of the article can be non-destructively diagnosed using a simple system. Further, defects can be identified of factor-by-factor basis.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: February 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Takezawa, Jun'ichi Katagiri, Hiroshi Shoji, Kenichi Ootaka
  • Patent number: 6853639
    Abstract: An information relay device connected between a plurality of logical or physical networks for performing an operation for relay of information between the networks is provided with a transmit/receive processing unit for receiving a general purpose multicast message from one of the plurality of networks and transmitting a multicast message to at least one of the plurality of networks, and a protocol conversion processing unit for converting, in the case where the general purpose multicast message received by the transmit/receive processing unit is a multicast protocol message of a certain level layer, the multicast protocol message of the certain level layer into a multicast protocol message of another level layer.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: February 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Watanuki, Shinji Nozaki