Patents Represented by Attorney Mattingly, Stanger & Malur, P.C.

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  • Information display device and display control device for construction machine
    Patent number: 6826465
    Abstract: An information display unit is provided inside a cab of a hydraulic excavator and has a display portion capable of displaying plural kinds of information including body information and maintenance information. A screen image has one main screen and a plurality of sub-screens. The main screen displays information regarding one of a plurality of information categories in detail and the plurality of sub-screens respectively correspond to th plurality of information categories. The information category displayed on the main screen can be selected and changed with key manipulation made on an operating portion. As a result, plural kinds of information can be displayed in a combined and selective manner, and an operator is able to confirm the information with higher efficiency.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: November 30, 2004
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Hidefumi Ishimoto, Hiroshi Ogura, Hiroshi Watanabe, Hiroyuki Adachi, Tsuyoshi Sakyou
  • Semiconductor device
    Patent number: 6825548
    Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toru Fujioka, Isao Yoshida, Toshihiko Shimizu
  • Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
    Patent number: 6826720
    Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology, Corp.
    Inventors: Iwao Suzuki, Shuji Kikuchi, Fumie Kobayashi, Hideyuki Aoki
  • Mobile communication apparatus including dividers in transmitter and receiver
    Patent number: 6826388
    Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
  • Pump trouble diagnosing device for hydraulic drive device and display device of the diagnosing device
    Patent number: 6823289
    Abstract: Fault diagnosis of hydraulic pumps is made automatically during an actual operation of a working machine, particularly when there is a problem with horsepower limiting control of the hydraulic pumps. A controller 50 performs horsepower limiting control for a plurality of variable displacement hydraulic pumps 1 to 6. The controller 50 measures a pump delivery pressure and pump delivery rate of each hydraulic pump when the pump delivery rate reaches a maximum during operation of the hydraulic drive system based on their detected values, collects the measured values as fault diagnostic data, and then compares a calculated target pump delivery rate with the collected pump delivery rate to decide if there is a fault of the hydraulic pump.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: November 23, 2004
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Hirotsugu Kasuya, Yutaka Watanabe, Masami Ochiai
  • Logic circuit whose power switch is quickly turned on and off
    Patent number: 6822476
    Abstract: The present invention is to provide a logic circuit which assures short-circuit current reduction by using a gate which uniquely fixes the level of each node and also reduces leakage current so that the power is turned on and off quickly. Logic gates of the subject logic circuit are divided into first-type logic gate and second-type logic gates. The first-type logic gate outputs high potential under the specific status and the second-type logic gate outputs low potential under the specific status. Under the state that the high potential is supplied to the first-type logic gates and the low potential is supplied to the second-type logic gates, the power switch MOS is turned on. Further, in case of the adder, the specific status is equal to selecting a constant as an input of the adder. For general logic circuit, specific flip-flops are introduced to implement this specific status.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corporation
    Inventor: Fumio Arakawa
  • Cellular mobile telephone apparatus
    Patent number: 6823182
    Abstract: A cellular mobile telephone apparatus has circuits for generating massages, a storage circuit for storing messages, and a transmitter/receiver circuit for transmitting a message. When the user of the cellular mobile telephone apparatus cannot immediately respond to an incoming call, a desired one of a plurality of previously generated and stored messages can be transmitted to a calling party through simple key manipulations or by other means.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: November 23, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazutoshi Higuchi, Katsuo Ogawa, Fumitaka Itoh, Yasuaki Takahara, Teiji Okamoto
  • Method and apparatus for scanning transmission electron microscopy
    Patent number: 6822233
    Abstract: A scanning transmission electron microscope (STEM) has an electron source for generating a primary electron beam and an electron illuminating lens system for converging the primary electron beam from the electron source onto a specimen for illumination. An electron deflecting system is provided for scanning the specimen with the primary electron beam. The STEM also has a scattered electron detector for detecting scattered electrons transmitted through the specimen. A projection lens system projects the scattered electrons onto a detection surface of the scattered electron detector. An image displaying device displays the scanning transmission electron microscope image of the specimen using a detection signal from the scattered electron detector. A detection angle changing device for establishes the range of the scattering angle of the scattered electrons detected by the scattered electron detector.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: November 23, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kuniyasu Nakamura, Hiroshi Kakibayashi, Mikio Ichihashi, Shigeto Isakozawa, Yuji Sato, Takahito Hashimoto
  • Web system having clustered application servers and clustered databases
    Patent number: 6820085
    Abstract: The present invention improves the scalability of application servers and database servers in Web systems, thereby providing higher cost-performance Web systems. The session state of an application is stored in a clustered cache database as required. This enables another application running on an arbitrary cluster server to read the stored session state from the clustered cache database to continue the processing of the application. In addition, a cache database cluster in which data can be updated on the cluster servers is configured, thereby providing a mechanism of causing them to synchronize with the database servers as necessary. Furthermore, a mechanism of adding cache databases to the cache database cluster, thereby enabling the system to respond to an increase in database access load.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Itaru Nishizawa, Nobutoshi Sagawa
  • Image display mechanism and image display device
    Patent number: 6817720
    Abstract: In order to prevent dust from sticking to the LCD panel, to prevent the LCD panel from being heated and to suitably adjust the position of the LCD panel, a duct is provided between cooling means for a light source and cooling means for a LCD panel to send cooling air from the LCD panel side to the light source side. Therefore, a light incidence/reflection plane of the LCD panel is disposed in an almost hermetically closed space and an optical path from an integrator lens to the LCD panel is formed in the almost hermetically closed space.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Mikio Shiraishi, Yasuo Otsuka, Toru Numata
  • Semiconductor device and method for fabricating the same
    Patent number: 6818949
    Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: November 16, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Radioactive waste treatment facility
    Patent number: 6818188
    Abstract: An injection and solidification operation as well as a kneading and solidification operation can be performed by a single facility. A decreased amount of radioactive secondary waste is generated. A solidifying agent paste is prepared by kneading a solidifying agent and additive water. The solidifying agent paste is injected into a solidifying container. The radioactive waste is charged into the solidifying container and kneaded.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: November 16, 2004
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Tooru Kawasaki, Atsushi Yukita, Masato Ohura, Yasuo Yatou
  • Semiconductor element and process for manufacturing the same
    Patent number: 6818914
    Abstract: A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Ishii, Kazuo Yano, Koichi Seki, Toshiyuki Mine, Takashi Kobayashi
  • Semiconductor integrated circuit device and microcomputer
    Patent number: 6819158
    Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: November 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Mizuno, Takahiro Nagano, Yoshinobu Nakagome
  • Semiconductor integrated circuit device
    Patent number: 6815761
    Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Toshiaki Nishimoto, Takashi Aoyagi, Shogo Kiyota
  • Elliptic curve generating method and device, elliptic encryption system and recording medium
    Patent number: 6816594
    Abstract: It is an object of the present invention to provide a method and an apparatus for generating a safe normal form elliptic curve transformable to a Montgomery type elliptic curve as well as to provide an elliptic curve cryptosystem and a storage medium therefor. To achieve the above object, conditions concerning a curve order are extracted from criteria for transformability of a normal form elliptic curve to a Montgomery type elliptic curve and are given in a curve parameter generator incorporating a transformability judgement unit. Furthermore, to generate a curve having a cofactor of 4, the condition whether a curve order is divisible by 8 is given.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventor: Katsuyuki Okeya
  • BICMOS semiconductor integrated circuit device and fabrication process thereof
    Patent number: 6815822
    Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: November 9, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Masao Kondo, Katsuyoshi Washio, Eiji Oue, Hiromi Shimamoto
  • Composite magnetic head arranged so the reproducing elements do not overlap a pole of a recording element
    Patent number: 6816344
    Abstract: A conventional magnetic head has a structure, in which a MR element and a recording element are stacked. The influence of a recording magnetic field on the magnetically sensitive portion of a reproduction element is lessened and the performance of the MR element is stabilized. Also, the reliability of the magnetic disk drive using a MR element is enhanced. The magnetic disk drive uses a composite magnetic head, which has a plurality of reproduction elements arranged such that the magnetically sensitive layer of a reproduction element of the composite magnetic head does not overlap with the normal direction projection of the recording element, and which lessens the influence of a recording magnetic field on the magnetically sensitive portion of each reproduction element.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: November 9, 2004
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventor: Reijiro Tsuchiya
  • Electromagnet and actuating mechanism for switch device, using thereof
    Patent number: 6816048
    Abstract: An electromagnet includes a coil, a movable iron core adapted to move on the center axis of the coil, and a stationary iron core provided so as to cover the upper and lower surfaces and the outer peripheral surface of the coil. A permanent magnet is arranged in a gap surrounded by the movable iron core and the stationary core.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: November 9, 2004
    Assignees: Hitachi, Ltd., Hitachi Engineering & Services, Co., Ltd.
    Inventors: Ayumu Morita, Yasuaki Suzuki, Masato Yabu, Tooru Tanimizu, Yozo Shibata, Takashi Kadowaki
  • Gas turbine combustor and operating method thereof
    Patent number: 6813889
    Abstract: A gas turbine combustor has a combustion chamber into which fuel and air are supplied, wherein the fuel and the air are supplied into said combustion chamber as a plurality of coaxial jets.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Inoue, Tomomi Koganezawa, Nariyoshi Kobayashi, Isao Takehara