Patents Represented by Attorney, Agent or Law Firm McCracken and Frank
  • Patent number: 8350361
    Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Tsung Chiu, Ying-Te Ou, Meng-Jen Wang
  • Patent number: 8333273
    Abstract: A device for receiving and transporting objects in a direction substantially different from the vertical is disclosed. The device includes a conveyor belt arranged in a transport direction and a row of flexible elements attached alongside and above the conveyor belt. Each row of flexible elements is inclined downwards, so as to present less mechanical resistance to a force oriented downwards than upwards. The device also includes a transport belt coupled to the conveyor belt wherein each row of flexible elements is fixed to the transport belt.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: December 18, 2012
    Assignee: Visar
    Inventor: Olivier Kleynen
  • Patent number: 8328349
    Abstract: Methods for controlling application of a substance to a substrate involve the use of a gating agent that blocks the substance from the substrate. The methods may utilize ink jet technology to apply the gating agent directly to the substrate or to an intermediate surface. The gating agent composition includes a nonionic surfactant, and water. The gating agent composition does not contain a discernable amount of dye, pigment or other colorant agent.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 11, 2012
    Assignee: Moore Wallace North America, Inc.
    Inventors: Kevin J. Hook, Theodore F. Cyman, Jr., Lawrence Pilon, Jeffrey Zaloom
  • Patent number: 8322047
    Abstract: A drying unit includes a frame having an air box mounted thereon, wherein the air box includes an intake port and an exhaust port. A plurality of rollers define a web path within the frame and a heat source is removably attached to the frame, wherein removal of the heat source does not require removal of a web from the web path.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 4, 2012
    Assignee: Moore Wallace North America, Inc.
    Inventors: John R. Soltysiak, Henderikus A. Haan, Theodore F. Cyman, Jr., Anthony V. Moscato
  • Patent number: 8314490
    Abstract: The present invention relates to a chip having a bump and a package having the same. The chip includes a chip body, at least one via, a passivation layer, an under ball metal layer and at least one bump. The via penetrates the chip body, and is exposed to a surface of the chip body. The passivation layer is disposed on the surface of the chip body, and the passivation layer has at least one opening. The opening exposes the via. The under ball metal layer is disposed in the opening of the passivation layer, and is connected to the via. The bump is disposed on the under ball metal layer, and includes a first metal layer, a second metal layer and a third metal layer. The first metal layer is disposed on the under ball metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. As the bumps can connect two chips, the chip is stackable, and so the density of the product is increased while the size of the product is reduced.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: November 20, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Kuo-Pin Yang
  • Patent number: 8305184
    Abstract: Surge arrester with a module 1, 3, 9, 25, which comprises a stack of varistor blocks 1, two end armatures, between which the stack of varistor blocks 1 is held, a plurality of reinforcing elements 9, which extend between the end armatures 3 and are fixed to said end armatures, the reinforcing elements 9 surrounding the stack of varistor blocks, and at least one stabilizing disc 25, which is arranged between two varistor blocks 1 in the stack and guides the at least one reinforcing element 9, and with an outer housing 5 with screens, in which outer housing the module is at least partially accommodated. In the case of the surge arrester according to the invention, the outer housing is designed in such a way that the module is accommodated without any gas, liquid or volumes or cavities therebetween. Furthermore, each of the stabilizing discs 25 is arranged in the region of one of the screens 7.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: November 6, 2012
    Assignee: Tridelta Uberspannungsableiter GmbH
    Inventors: Hartmut Klaube, Hubert Lauritsche
  • Patent number: 8297549
    Abstract: A rotor for a helicopter, having a drive shaft rotating about a first axis; a hub angularly integral with the drive shaft about the first axis; and at least two blades projecting from the hub, on the opposite side to the first axis, and extending along respective second axes crosswise to the first axis; each blade is movable with respect to the hub and the other blades about a respective fourth axis parallel to the first axis, about the respective second axis, and about a respective third axis crosswise to the first and respective second axis; the rotor also has a number of first dampers for damping vibration associated with at least oscillation of the relative blades about the respective fourth axes; the first dampers are connected to one another and each to a relative blade; and, in a radial direction with respect to the first axis, at least one first damper is located between the first axis and the fourth axis of the relative blade.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: October 30, 2012
    Assignee: Agusta S.p.A.
    Inventors: Fabio Nannoni, Pierre Abdel Nour, Dante Ballerio
  • Patent number: 8292229
    Abstract: An aircraft capable of hovering, and having a fuselage defining an access opening; driving means for operating a rescue cradle; and a first wall movable between a closed position engaging a first portion of the opening, and a first open position allowing access to the first portion of the opening. The aircraft has a member connected functionally to the first wall and in turn having at least one flat surface; and the member is movable with respect to the wall into a first position, in which the flat surface defines a supporting surface for the cradle when the first wall is in the first open position.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: October 23, 2012
    Assignee: Agusta S.p.A.
    Inventors: Santino Pancotti, Dante Ballerio
  • Patent number: 8295387
    Abstract: The invention relates to an improved encoding and decoding method with at least two pairs of orthogonal sequences for improving the time necessary for calculating the coefficients of the filter for the purpose of reducing the data overload in communication systems by half by means of the emission of both sequences simultaneously and the emission of the result by means of quadrature modulation to a transmission medium.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: October 23, 2012
    Assignee: GCM Communications, Parque cientifico Tecnoalcala
    Inventor: Vicente Diaz Fuente
  • Patent number: 8289538
    Abstract: A system for managing a job in accordance with a job specification and job content includes a database that stores device information and a configuration engine. The configuration engine is responsive to the job specification and the database and identifies one or more device configurations that are capable of producing the job. The system also includes a controller that is responsive to a selection from the one or more device configurations to produce a command stream in a format compatible with the selection.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 16, 2012
    Assignee: Moore Wallace North America, Inc.
    Inventors: Theodore F. Cyman, Jr., Robert D. Doyle, William D. Romanowich, Paul A. Coniglio, Nancy A. Lee
  • Patent number: 8288854
    Abstract: The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: October 16, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao-Fu Weng, Yi-Ting Wu
  • Patent number: 8288853
    Abstract: A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: October 16, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Patent number: 8290570
    Abstract: A method, system and device for tracking an anatomical structure includes a section having a small cross section relative to the length, a first end of the section having a tip capable of being removably attached to the anatomical structure; and a second end of the section that has two position-indicating sensors located thereon. The position-indicating sensors are tracked and displayed by the system.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: October 16, 2012
    Assignee: Stryker Leibinger GmbH & Co., KG
    Inventors: Harald Hoppe, Jose Luis Moctezume de la Barrera
  • Patent number: 8274133
    Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package comprises a substrate, a first metal layer, a first dielectric layer, a first upper electrode, a first protective layer, a second metal layer and a second protective layer. The substrate has at least one via structure. The first metal layer is disposed on a first surface of the substrate, and comprises a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first capacitor. The second metal layer is disposed on the first protective layer, and comprises a first inductor. The second protective layer encapsulates the first inductor.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: September 25, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 8273803
    Abstract: Compositions and methods of their use to adhere a variety of materials together are disclosed herein. The compositions include at least tetra calcium phosphate, an effective amount of a compound that is structurally similar to phosphoserine, and can be mixed with an aqueous solution. The compositions provide adhesive and cohesive strength in both wet and dry environments and exhibit significant bond strength upon curing.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: September 25, 2012
    Assignee: Howmedica Osteonics Corp.
    Inventors: Venkat R. Garigapati, Brian J. Hess, Jon Ahola
  • Patent number: 8272546
    Abstract: A support belt which includes openings to connect with and attach to the waist support of existing mei tai baby carriers. The support belt further comprises padding within its inner components and vertical stitching to enable the belt to fold to allow it to encircle the waist of a wearer. The support belt can also include attachments such as a child harness, as well as storage and attachment elements for storing and connecting additional items.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: September 25, 2012
    Assignee: Catbird Baby, Inc.
    Inventor: Beth Warrell Leistensnider
  • Patent number: 8267697
    Abstract: The invention relates to educational equipment comprising a plurality of information support means (1) having identical dimensions but bearing at least partly different information. According to the invention, each support means (1) takes the form of a board comprising an outer frame (2) into which are inserted, removably and with friction, at least two inner frames (3), into each of which are inserted, removably and with friction, at least two labels (4) bearing the information.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: September 18, 2012
    Inventor: Jean-Loup Druon
  • Patent number: 8263493
    Abstract: The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: September 11, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsueh-An Yang, Pei-Chun Chen, Chien-Hua Chen
  • Patent number: 8252629
    Abstract: The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 28, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Chung Yee, Meng-Jen Wang
  • Patent number: D668948
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 16, 2012
    Assignee: S. A. Gems Distributors Inc.
    Inventor: Christopher W. LaTrobe