Patents Represented by Attorney, Agent or Law Firm McGinn & Gibb, P.C.
  • Patent number: 5883629
    Abstract: A method for generating a computer representation of a two-dimensional or three-dimensional object featuring recursive and anisotropic division of the representation. A bitree approach is provided for successively dividing into two equal parts any portion of the computer representation of the object. Each subdivision into two parts is accomplished by dividing the portion either horizontally or vertically. The method is implemented over a user interface to an information handling system comprised of one or more processors, a memory system, I/O devices, and an operating system program. Each subdivision of the computer representation of the object is comprised of a data structure that is efficiently stored in the memory system and dynamically updated to contain information about its neighboring subdivisions in order that balancing can be effectively achieved.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: March 16, 1999
    Assignee: International Business Machines Corporation
    Inventor: Jeffrey Bowman Johnson
  • Patent number: 5883818
    Abstract: Modeling of propagation delay and output transition time by use of fitting functions comprised of standard Taylor series and inverse powers is disclosed. These components are used as a basis for generating an equation that predicts circuit performance over a wide range of input transition and output capacitive loads. The present invention includes a computer implemented method for adding functions to the fitting functions or removing functions from the fitting functions until an acceptable error limit has been reached.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: March 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Bijan Salimi, David Bruce White
  • Patent number: 5881284
    Abstract: A computer system and method of scheduling a job in a clustered computer system having a plurality of clusters and a global storage, stores an inputted job in a job queue allocated in the global storage, selects a job to be executed, and executes the selected job in a cluster. The job selection is activated by one of a job completion, a job arrival, and a measurement completion. Upon the job selection, if the resource utilization is low, then a new job is requested. However, if the resource utilization is high, then a new job is not requested.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventor: Hidehito Kubo
  • Patent number: 5880822
    Abstract: A light wave distance measuring apparatus includes a light-sending optical system and a light-receiving optical system, which are preferably arranged to be parallel to each other. Intensity-modulated light of the light-sending optical system is transformed into parallel rays of light and projected towards a target, reflected back towards the measuring apparatus and detected by the light-receiving optical system in order to calculate the distance of the target from a reference point.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: March 9, 1999
    Inventor: Akio Kubo
  • Patent number: 5880995
    Abstract: A nonvolatile semiconductor storage includes a memory cell array provided with a plurality of memory cell transistors including a plurality of blocks and arranged in each block as a matrix with rows and columns, and with a plurality of N-channel transistors whose sources are connected to an auxiliary bit line common to the drains of the memory cell transistors of each column. A word line is connected to control gates of memory cell transistors of each row of the memory cell array in common. A main bit line is connected to drains of N-channel transistors of each column of the memory cell array in common. An X decoder includes a predecoder for selecting a predetermined word line in accordance with an input address, a block decoder for selecting a block by outputting a block selection signal to the N-channel transistor of a predetermined block in accordance with an input address, and a main decoder for selecting a predetermined word line in accordance with the output of the predecoder or the block decoder.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventor: Hiroyuki Kobatake
  • Patent number: 5875446
    Abstract: Topically relevant objects in an object database are first identified using any generally known methods to obtain a set of topically relevant objects (topically relevant set). Parents, and in alternative embodiments other ancestors, of one or more of the topically relevant objects are identified according to directional structural relationships that the parents have with respect to the topically relevant objects. These objects form a set of structurally relevant objects (structurally relevant set). In some embodiments, the user query identifies one or more of these structural relationships. The topically relevant objects are then organized under one or more of their respective parents to form a hierarchy level of both (topically relevant and structurally relevant) sets of objects. In some preferred embodiments, the process can iterate to create more than one hierarchy level.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Eric William Brown, Rong Nickle Chang, Hamed Abdelfattah Ellozy, John Martin Prager, Edward Cholchin So
  • Patent number: 5875473
    Abstract: In a multi-processor system, a page descriptor can be updated in a memory coupled to a processor without stopping operations of other processors. Each processor has a page descriptor comparator including a calculated address register which stores a physical page address for an address calculation, and an updated address register which stores a physical page address to be updated. The page descriptor comparator also has a reset page descriptor (RSTPD) mode register which indicates a mode of the processor, and a coincidence detector. If the RSTPD mode register is active, the coincidence detector detects coincidence between the calculated address register and the updated address register.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: February 23, 1999
    Assignee: NEC Corporation
    Inventor: Osamu Higuchi
  • Patent number: 5862139
    Abstract: A receiver removes a direct current (DC) offset component from a received Code Division Multiple Access (CDMA) spread spectrum signal. The DC offset is attributed to both spreading code imbalance as well as conversion between analog and digital formats. In operation, received data is de-spread using an appropriate de-spreading code. Thereafter, a DC offset removing circuit employs a positive/negative counter counting each occurrence of positive and negative chips to produce a chip imbalance for each chip in the spreading code. The measured imbalance is multiplied by the received data signal, an RF component of this multiplied output is removed by a low-pass filter, and thereafter, the signal is again multiplied by the chip imbalance. The DC offset components in the received signal are removed by subtracting the second multiplied signal from the received data signal.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: January 19, 1999
    Assignee: NEC Corporation
    Inventor: Shuzo Yanagi
  • Patent number: 5860108
    Abstract: In a clustered multi-processor system and method, first and second clusters are connected between first and second directories. The first directory checks whether an address of a request on a first system bus coincides with an address of a request from the second directory. When the first directory detects the coincidence, the first directory cancels the request on the first system bus, and reissues the request. Since the first system bus and a second system bus have a different clock phase, the requests are checked without overlapping.
    Type: Grant
    Filed: April 25, 1996
    Date of Patent: January 12, 1999
    Assignee: NEC Corporation
    Inventor: Koichi Horikawa
  • Patent number: 5853251
    Abstract: A manual printing device manually scanned across a recording medium to record images in ink on the recording medium, the device including: a recording unit for recording images in ink on the recording medium; an ink supply unit including an ink tank filled with ink and an ink tube for supplying ink from the ink tank to the recording unit; an ink tube valve disposed along the ink tube and for controlling supply of ink from the ink tank to the recording unit; and an ink tube valve drive unit for opening the ink tube valve when the recording unit is in confrontation with the recording medium and closing the ink tube valve when no recording medium is in confrontation with the recording unit.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: December 29, 1998
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Koji Imai
  • Patent number: 5852586
    Abstract: To obtain high access speed regardless of a structure and operating characteristics of an external central processing unit (CPU), a synchronous dynamic random access memory (DRAM) system includes first and second DRAM cell arrays, and a first address generator for outputting a first address and a second address respectively to the first and second DRAM cell arrays simultaneously in a first mode. In a second mode, the first address generator outputs the first address and the second address respectively to the first and second DRAM cell arrays sequentially.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: December 22, 1998
    Assignee: NEC Corporation
    Inventor: Mamoru Fujita
  • Patent number: 5848006
    Abstract: A drive circuit for a semiconductor memory device in which a plurality of memory cell arrays are driven by a divisional decode system, includes a single, row address decoder including a plurality of address latch circuits for holding an address signal for normal operation via a first logic gate unit, and a plurality of normal/redundancy switching circuits for inputting therein held data, and an address signal for redundancy purposes, and for switching the input signal in response to a judging signal for redundancy purposes. The outputs of the switching circuits are activated through a second logic gate unit into which a row address enable signal is inputted. Thus, a driver selection signal during normal operation and a driver selection signal during a redundancy operation are commonly used. As a result, a total number of wiring lines and the number of driver circuits, as well as the chip area, are reduced.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: December 8, 1998
    Assignee: NEC Corporation
    Inventor: Kyoichi Nagata
  • Patent number: 5844847
    Abstract: In a nonvolatile floating gate memory cell array, memory cells can become over-erased wherein their threshold voltage becomes near zero volts or even slightly negative. To correct over-erased cells and raise their threshold voltages to a normal level, a nonvolatile memory includes a control circuit for applying a programming voltage (approximately 5V) to the bit lines of the memory cell array and a lower voltage (approximately 2V) to the word lines of the memory cell array. The lower voltage is selected to be less than the threshold voltage (e.g., 3V) for a normal cell such that normal cells are not affected. However, the cells in an over-erased state will become active by the lower threshold voltage and begin conducting. A channel current flows to the over-erased memory cells and channel hot electrons induced by this channel flow into the floating gate of the memory cell raises the threshold voltage (VTM) of the memory cell to a normal level.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: December 1, 1998
    Assignee: NEC Corporation
    Inventor: Hiroyuki Kobatake
  • Patent number: 5841929
    Abstract: A light wavelength filtering circuit in a wavelength-division multiplexing light communication system minimizes transmission loss in the waveguide after wavelength discrimination by having a linear output waveguide added to an output end of a light wavelength discriminating element, at which a signal having a long wavelength is outputted. A curved output waveguide is added to the rear stage of the output end at which a signal having a relatively short wavelength is outputted. Hence, a radiation loss at the output waveguide at the output end is minimized, while a space between the output light waveguides is being widened. Additionally, a core layer bandgap wavelength at the output waveguide of the long wavelength signal is set to be longer than a core layer band gap wavelength in another region.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: November 24, 1998
    Assignee: NEC Corporation
    Inventors: Keiro Komatsu, Masako Hayashi, Kiichi Hamamoto, Tatsuya Sasaki, Takeshi Takeuchi
  • Patent number: 5829893
    Abstract: A printing device includes a casing housing a sheet-feed mechanism for transporting a print medium and a carriage transporting mechanism for reciprocally moving a carriage in a main scanning direction. A print unit having a print head is detachably attached to the carriage. The print unit is capable of printing whether attached or detached from the carriage. A detection unit is provided for determining whether the print unit is attached to the carriage. The casing can be formed with a hollow space in which the print unit can be stored when the print device is not being used.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: November 3, 1998
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Naohisa Kinoshita, Yoshiki Katayama, Motoaki Yamanashi, Masatoshi Kokubo
  • Patent number: D402693
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: December 15, 1998
    Assignee: Kotobuki & Co., Ltd.
    Inventor: Yuki Sunaga
  • Patent number: D402695
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: December 15, 1998
    Assignee: Kotobuki & Co., Ltd.
    Inventor: Hiromichi Izushima
  • Patent number: D403705
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: January 5, 1999
    Assignees: Kotobuki & Co., Ltd., BIC Corporation
    Inventors: Hiromichi Izushima, Gary Prushansky
  • Patent number: D404765
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: January 26, 1999
    Assignee: Kotobuki & Co., Ltd.
    Inventors: Hiromichi Izushima, Gary Prushansky
  • Patent number: D405468
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: February 9, 1999
    Assignee: Kotobuki & Co., Ltd.
    Inventor: Hiromichi Izushima