Abstract: In a semiconductor memory including a memory cell array and a redundant memory cell array, a defective memory cell address detecting circuit includes a precharge transistor for precharging a COMP signal line of outputting a signal indicative of whether or not an input address is an address of the defective memory cell, and a plurality of detection transistors connected in parallel to the COMP signal line. Each of the detection transistors has a gate connected to receive, through a wired connection, a corresponding bit and its inverted bit of bits of the input address signal. Thus, the number of detection transistors connected in parallel to the COMP signal line can be reduced to a half of the number required in the prior art.

Abstract: A low-cost non-contact type charging device having excellent uniform charging performance and long stable charging characteristic includes an insulating support body having an insulating surface, first electrodes, to which a first voltage is applied, and second electrodes, to which a second voltage is applied. The first electrodes and the second electrodes, isolated from each other, are alternately formed, in non-parallel to a relative moving direction between a charging member and a charged body. Further, the first electrodes and the second electrodes are provided at respective positions in a width in the relative moving direction of the charging member, and moved close to the charged body in a non-contact state.

Abstract: An improvement to a phase controlled mechanical oscillator consists of a balancing network which generates a feedback signal from two different input signals with adjustable weights. One of these input signals is directly derived from the oscillator signal, the other is derived from a phase tracking loop. Using the balancing network, adjustments can be made to adapt the feedback to the mechanical properties, in particular to the Q factor, of the oscillator. In a preferred embodiment, all major components are working at an intermediate frequency level, generated by mixing the oscillator frequency with a reference frequency. As a major advantage of this (heterodyne) mixing, the bandwidth of any applied frequency detector can be narrowed, thus increasing the achievable signal-to-noise ratio.

Abstract: A method and data transfer control unit for controlling a data transfer between a calling device and a called device, includes a first device for sending, from the calling device to the called device, a control signal for informing the called device of a data transfer format. A second device sends, from the called device to the calling device, a response signal for defining whether the data transfer format defined by the control signal has a predetermined state.

Abstract: A magnesium-doped semiconductor layer expressed by general formula Al.sub.x Ga.sub.1-x N (where 0.ltoreq.x.ltoreq.1) is formed on a substrate. Thereafter, on the semiconductor layer, a plurality of semiconductor layers (including an activation layer) expressed by general formula In.sub.x Al.sub.y Ga.sub.1-x-y N (where 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, 0.ltoreq.x+y.ltoreq.1) are formed. The crystalline characteristics of semiconductor layers including a light emitting layer of a gallium nitride semiconductor light emitting device having a magnesium-doped gallium nitride semiconductor layer are good. Thus, in the case that the light emitting device is a laser device, it can be expected that the oscillating threshold value of the laser device becomes low. In the case that the light emitting device is a light emitting diode, it can be expected that the light emitting efficiency of the light emitting diode becomes high.

Abstract: A control field in a store-in cache memory in a multi-processor system includes a valid bit, an exclusive bit, and a clean bit. An error in the control field is not only detectable but also correctable by a control field correction circuit. The control field correction circuit includes a mode register holding inhibit correction flags, inhibit correction-in-part flags, and detect inconsistency flags.

Abstract: For enabling to obtain automatically a proper identifier of a remote terminal and to assign an identification number to the remote terminal in order to performing supple communication control of a data transmission system wherein upward communication is performed according to a TDMA system and downward communication is performed according to a TDM system making use of cells having fixed length; a local station of the system comprises: a command-cell generation timer (112) for generating a command-cell generation trigger periodically, a command-cell generating unit (113) for generating a command cell to be downward transmitted every time the command-cell generation trigger is supplied by writing an available identification number therein, a window generation timer (111) for enabling a window signal every time the command-cell generation trigger is supplied for inhibiting transmission of upward cells from the remote terminals whereto identification numbers are assigned, a control-data-cell generating/terminatin

Abstract: Apparatus and method for testing the integrity of computer alarm systems which can be part of a computing network, includes testing the computer alarm system by simulating an attack on the computing network including the alarm system itself. Thereafter, information, pertaining to the status of the computing network alarm system attendant upon the simulated attack, is registered.

Abstract: A semiconductor integrated circuit device has a protective structure between a semiconductor chip and a ball grid array, and the protective structure has a thin polyimide film bonded to the surface of the semiconductor chip and a thick stress relaxation layer covering conductive strips connected between pads on the surface and the ball grid array; when thermal stress is exerted on the ball grid array, the thick stress relaxation layer allows said ball grid array to move so as to take up the thermal stress.

Abstract: To increase access speed, a single-chip computer system having a direct memory access (DMA) mode, includes a central processing unit (CPU) for executing instructions, a first bus connected to the CPU, a memory array connected to the first bus, for storing data, a buffer connected to the first bus, a second bus connected to the buffer, and a communication circuit, connected to the second bus, for receiving and outputting data. The buffer connects the first bus to the second bus when the DMA mode is executed, and disconnects the first bus from the second bus when the DMA mode is not executed.

Abstract: A light beam scanner includes a supporting substrate. Fixed electrodes of a first set are provided on the supporting substrate to oppose to each other. A mirror is provided between the fixed electrodes, has torsion bars physically connected to the supporting substrate and a mirror electrode section in end portions of the mirror opposing to the fixed electrodes at least. The mirror rotatably vibrates between an upper position of the one fixed electrode and a lower position thereof by torsion force of the torsion bars and electrostatic force due to the voltage using the torsion bars as a rotation axis, when a voltage is applied between one of the fixed electrodes and the electrode section.

Abstract: A semiconductor memory device comprises memory cells at least one pair of bit lines; word lines for taking out information from the memory cells into the pair of bit lines; sense amplifiers for detecting potential difference between the pair of the bit lines and amplifying it to a predetermined level; a write amplifier into which write data from outside are inputted and which drives the pair of data path lines for complementary data; inputting means and for providing the pair of data path lines to the respective pair of bit lines; and one or more amplifying means and for detecting potential difference between the pair of data path lines and amplifying it to a predetermined level. The sense amplifier in a sense amplifier area corresponding to the dummy cell area for treating the end portion of the memory cell array area and a word line-suspending section is used to drive the pair of data path lines in the middle of the wiring of the pair of data path lines, thereby carrying out high speed writing.

Abstract: A software management system is provided which enables the configuration of a software system to be checked on a specification level and the difference between two software systems to be identified easily. A system name and a system revision for each client to which the system has been released as well as a specification name and a specification revision for each system revision are registered in a configuration storage. And the name, all of the existing revisions and contents of each specification are registered in a specification storage. A data reference means outputs the contents of the configuration storage or the specification storage to a display device according to a data reference request from an input device such as a keyboard, and also outputs the difference in the name and revision of the specifications of two software systems input from the input device, and/or the contents of the specifications.

Abstract: To use both an array of main memory cells and an array of redundant memory cells efficiently during a block writing operation, a memory system for performing the block writing operation includes a bit line activator activating at least one bit line of bit lines of the array of main memory cells and at least one bit line of bit lines of the array of redundant memory cells simultaneously during the block writing operation.

Abstract: A semiconductor dynamic random access memory device enters into a test mode at a WE/CAS-Before-RAS timing, and selectively carries out self-diagnostic functions under application of a super voltage; when the super voltage is applied to a signal pin, a super voltage detecting circuit checks it to see whether the potential level exceeds the positive power voltage, and supplies a control signal representative of detection of the super voltage to a test control signal generating circuit for producing a test entry signal and to a data pin through a selector so as to allow an analyst to confirm the entry into the self-diagnostic function.

Abstract: A semiconductor dynamic random access memory device has first open bit lines arranged in parallel and second open bit lines respectively paired with the first open bit lines so as to form bit line pairs and a sense amplifier shared between the bit line pairs so as to increase the magnitude of a potential difference indicative of a data bit sequentially supplied from the bit line pairs, and either high or low level indicative of the data bit is supplied to both first and second bit lines of the selected bit line pair upon completion of the sense amplification, thereby equalizing electric influence on the adjacent open bit lines.

Abstract: An image forming device includes: a recording unit which prints an image on a recording medium; a memory unit which stores image information for pixels forming the image; a speed detection unit which detects movement speed of the recording unit; a speed comparison unit which compares the movement speed detected by the speed detection unit with a preset reference speed to determine whether the movement speed is faster or slower than the reference speed; and a control unit which controls drive of the recording unit in synchronization with the movement speed detected by the speed detection unit to print the image based on the image information stored in the memory unit and which performs processes so that the recording unit prints the image in a density dependent on whether the speed comparison unit determines that the movement speed is faster or slower than the reference speed.

Abstract: In a semiconductor memory including a plurality of synchronous DRAMs controlled by one common memory controller, each of the synchronous DRAMs has first and second terminals for receiving a reference clock supplied from the memory controller. A signal line for this reference clock is laid out in such a manner that the signal line is connected from the memory controller firstly to the first terminal of the most remote synchronous DRAM, and then, to respective first terminals of the remaining synchronous DRAMs, in order, towards the nearest synchronous DRAM and further, to the second terminal of the nearest synchronous DRAM, and then, to respective second terminals of the remaining synchronous DRAMs, in order, towards the most remote synchronous DRAM.