Abstract: A semiconductor device comprising an insulating film at least partially containing a fluorine-containing film, formed above a semiconductor substrate, and a titanium nitride film formed on the insulating film. The above titanium film functions as a barrier metal film for barriering the diffusion of fluorine (F) atoms.

Abstract: A keyboard apparatus is provided for small and lightweight computers and the like. Keyswitches and a keyboard assembly comprise a sheet member having a plurality of key faces fixed thereon in a conventional keyboard arrangement. A plurality of cutouts are provided in the sheet member, partially surrounding each key face. A living hinge member is provided in the sheet member at one side of each key face. Each living hinge member includes a base section, an intermediate section, and a key face section. The former two and the latter two sections each interface at a living hinge. Depressing the key face causes the key face section to pivot about the living hinges to operate a corresponding set of electrical contacts, indicating operation of the key. A conventional rubber spring may transmit the pivot motion of the key face to the electrical contacts.

Abstract: A method suitable for use in a physical distribution network. The method comprises the steps of using a distribution resource planning (DRP) logic for providing estimates of at least one of projected future on-hand inventory and replenishment requirements; and, incorporating within the DRP logic an uncertainty of future demand for estimating at least one of future replenishment requirements and inventory levels in the physical distribution network.

Abstract: The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.

Abstract: A method and system are disclosed, for providing a user interface with a graphical user interface (GUI) computer system. The method comprising the steps of receiving a user input command signal, the signal including first and second signals, representative of movements of respective first and second user input mechanisms for two-dimensional movements, resolving the first and second signals from the user input command signal, operating a first displayed symbol based on the first signal, and operating a second displayed symbol based on the second signal. The invention is advantageously practiced in an environment in which the user has a plurality of two-dimensional movement input devices, such as a mouse having a joystick-type pointing device as well as the surface contact ball on its underside.

Abstract: An optical transmitter which employs a laser diode for emitting light has a temperature compensator connected parallel to the laser diode. The temperature compensator controls a drive current supplied to the laser diode such that an emission level of the laser diode is kept constant even when the ambient temperature around the laser diode changes.

Abstract: A lattice of a wiring or terminal pattern is varied at areas on a wiring board. The spacing of the wiring lattice is reduced only in a predetermined area for a device having many terminals. An alignment pattern is provided in the predetermined area. The spacing of the wiring lattice in the central portion of the wiring board may be the finest and may get gradually coarser toward the peripheral portion of the wiring lattice.

Abstract: An integrated circuit device cooling structure includes a wiring substrate, an integrated circuit device, a heat sink, and heat radiation vias. The integrated circuit device is mounted on the first surface side of the wiring substrate. The heat sink is fixed to the second surface of the wiring substrate and thermally coupled to the wiring substrate. The heat radiation vias are formed in the wiring substrate to transmit heat generated by the integrated circuit device to the heat sink.

Abstract: In a data erase operation of the present invention, a drain terminal is opened. A negative voltage of about -10 V and a voltage of about 5 V are applied to a cell gate and a source terminal, respectively. The voltage of about 1-2 V is applied to a P well terminal and an N well terminal. A ground potential is provided to a substrate. A voltage which is lower than the voltage of the source terminal and higher than the substrate voltage (ground voltage) is applied to a P well and an N well between a source diffusion layer and the substrate. Thus, an electric field generated between a source and a floating gate realizes the erase by means of F-N tunneling.

Abstract: An internal synchronous signal generating circuit outputs the internal synchronous signals ICLK1, ICLK2. A burst counter outputs an internal column address signal IADD and the lowermost internal column address signal IY0. A first and second D-F/Fs input an output of the input buffer and drives a first write bus (WBUS) in synchronization with the ICLK1. An inverting element inputs IY0. Inverting elements input outputs of the first and second D-F/Fs and drives a second write bus (WBUS). A transistor TG1 is connected between the first WBUS and second D-F/F. The gate is connected to the output of the first inverting element. A transistor TG2 is connected between the output of the second inverting element and second D-F/F with IY0 connected to the gate. A column decoder inputs IADD and outputs a column switch YSW. Sense amplifiers input the YSW and the second WBUS. A memory cell array is connected to the sense amplifiers through a bit line.

Abstract: In a semiconductor memory of the present invention, a group of electrode pads for connecting the semiconductor memory to the outside and assigned to a plurality of same functions are arranged on the surface of a memory pellet in both of the first and second quadrants divided by the center line of the memory pellet. With a single semiconductor pellet, there can be implemented both of face-up and face-down pellet mounting on a package.

Abstract: A writing instrument includes a tubular body, a guide sleeve, an outer sleeve, and a holder. The outer sleeve includes at least one groove on an inner surface thereof, and the guide sleeve includes at least one rib on a forward portion thereof to engage the groove of the outer sleeve. An inclined surface continuously inclining relative to the axial direction of the outer sleeve is formed at a rearward end portion of either side wall of the groove such that a width of the groove becomes wider in a direction of the rearward end. An inclined surface continuously inclining relative to the axial direction of the outer sleeve is formed at a forward end portion of either side wall of the rib such that a width of the rib becomes smaller in a direction of the forward end. An inclined angle of the inclined surface of the groove is not less than that of the inclined surface of the rib.

Abstract: Method and apparatus for realizing unusually sensitive and stable interferometric measurement capabilities. The apparatus comprises an optical interferometer with at least two optical outputs, the ratio of whose intensities can vary with a tuning parameter; and at least one detector, each of which is optically connected to the interferometer, and producing in aggregate at least two linearly-independent signals that depend on the light intensity and the tuning parameter, which are combined to produce a first measurement whose sensitivity to light intensity changes is substantially smaller than that of either of the two linearly-independent signals, and a second measurement whose sensitivity to the tuning parameter is substantially smaller than that of either of the two linearly-independent signals.

Abstract: At a transmitter side, signals are provided with a delay difference with a plurality of branches, coded multiplexed by spectrum spreaders and a combination unit, and transmitted by a single antenna. At a receiver side, the signals are received by a single antenna, and diversity branches are extracted and separated by first and second spectrum de-spreaders. They are subject to linear combination so that the mean square of the decision error signals is minimized. The output passes through an adaptive matched filter and an adaptive equalizer so as to provide an output from which interference waves are eliminated. Thus, interference is eliminated and diversity gain for a signal is ensured, while reducing the scale and cost of a system without using a plurality of antennae.

Abstract: An electronic device assembly includes a large-scale integrated circuit (LSI) chip mounted on a flexible substrate. The flexible substrate is connected to a second substrate via solder. The flexible substrate is also attached to the second substrate via a resin. When the assembly is manufactured, the solder is provided between the substrates. The resin fills an area between the substrates. The solder and the resin are heated simultaneously. The solder melts to electrically connect the substrates. The resin is set to mechanically couple the substrates.

Abstract: To avoid selecting multiple word lines, a memory system including a pulse word line method capability includes a decoder for activating one word line when a clock signal has an active level and for forcibly inactivating all word lines when the clock signal has an inactive level.

Abstract: A semiconductor dynamic random access memory device has memory cells each storing a piece of multiple-valued data equivalent to two-bit binary data in the form of electric charge, and sub-bit line pairs selectively connected to the memory cells use parasitic capacitors coupled thereto as charge accumulators weighted by two, wherein the piece of multiple-valued data transferred from the sub-bit line pair to a main bit line pair supplies a first potential level to one of the charge accumulators assigned to the most significant bit and a second potential level to another of the charge accumulators assigned to the least significant bit, and dummy cells are selectively coupled to the charge accumulators so as to make storage capacitance coupled to the charge accumulator assigned to the most significant bit twice as large as the storage capacitance coupled to the charge accumulator assigned to the least significant bit, thereby eliminating electrical influence of the storage capacitor of the selected memory cell fr

Abstract: A writing instrument includes a barrel having a substantially cylindrical body, the cylindrical body having a finger gripping area and an outer circumferential recess portion provided around the finger gripping area, a writing medium advancing mechanism axially movably disposed within the barrel, an actuating member provided at the outer circumferential recess portion for actuating the writing medium advancing means, the actuating member being engaged with the writing medium advancing mechanism, and a finger gripping member provided around the circumferential recess portion of the cylindrical body, the finger gripping member having an opening, the actuating member being exposed externally through the opening of the finger gripping member.

Abstract: A multi-layer ceramic module comprises a multi-layer ceramic substrate having an upper side and a lower side, at least one semiconductor chip mounted on the upper side of the substrate, a plurality of module pins projecting from the lower side of the substrate and at least one decoupling capacitor mounted on the lower side of the substrate between adjacent ones of the module pins.