Patents Represented by Attorney McGinn & Gibb, PLLC
  • Patent number: 7130141
    Abstract: An information processing assembly includes at least one heater suitable for information processing, and a controller for controlling the at least one heater by at least one of adjusting a power to the at least one heater to match a target power level, and changing a polarity of an electrical current supplied to the heater.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: October 31, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: S. Jay Chey, Hendrik F. Hamann, Martin Patrick O'Boyle, H. Kumar Wickramasinghe
  • Patent number: 7123323
    Abstract: In a liquid crystal display device having a pixel board on which light shielding film 3, first insulating film 10, semiconductor layer, second insulating film 11 serving as a gate insulating film and gate wires 4 are formed, a source region, a drain region and a channel region or both of a channel region and LDD (Light doped drain) region being formed in the semiconductor layer, the light shielding film 3 is made of a conductive material, and contact holes 6 for connecting each gate line and the light shielding film are provided in the neighborhood of the side surface of the channel region or/and the LDD region.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: October 17, 2006
    Assignee: NEC Corporation
    Inventors: Nobuaki Honbo, Kazuhide Yoshinaga, Hiroyuki Sekine
  • Patent number: 7121925
    Abstract: A method for dividing a semiconductor wafer into chips according to the present invention is a method for dividing a semiconductor wafer into a large number of semiconductor chips, the semiconductor wafer having a semiconductor layer formed on a substrate. A first method includes the step of forming a blast-resistant mask on a surface of the semiconductor wafer, the blast-resistant mask having a pattern for leaving a grid-like exposed portion as it is and the step of blasting a fine particular blast material to thereby form dividing grooves reaching a predetermined depth of the substrate in the grid-like exposed portion.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 17, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masaki Hashimura, Takao Sato, Koichi Ota
  • Patent number: 7085109
    Abstract: In a spin value type transducer including two magnetic shield layers, a patterned magnetoresistance element is in direct contact with one of the magnetic shield layers. A permanent magnet layer and an electrode layer are formed on the sides of the patterned magnetoresistance element.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: August 1, 2006
    Assignee: TDK Corporation
    Inventor: Nobuyuki Ishiwata
  • Patent number: 7084421
    Abstract: A light-emitting semiconductor device provides an active layer which comprises thirteen (13) layers that includes six (6) pairs of quantum barrier layers made of Al0.95In0.05N and quantum well layers made of Al0.70In0.30N, which are laminated together alternately. The semiconductor device may also comprise a quantum well layer having a high composition ratio of indium (In). Forming the quantum barrier layer and the quantum well layer to have a high composition ratio of indium (In) increases the lattice constant of the active layer of the semiconductor device.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: August 1, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shiro Yamazaki, Akira Kojima
  • Patent number: 7078980
    Abstract: The LC-VCO is provided with two negative resistance units and an LC circuit unit. The LC circuit unit has two output terminals. An inductor is connected between the output terminals, and a series of variable capacitors is connected in parallel with the inductor. In the LC circuit unit, a variable capacitor is connected between one of the output terminals and a node. Another variable capacitor is connected between the other output terminal and another node. Switches are connected between the nodes and a ground potential line, respectively, and between the nodes and a power supply potential line, respectively.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: July 18, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Yoshinori Muramatsu
  • Patent number: 7076242
    Abstract: A mobile station includes a wireless communication unit and Web function unit. The wireless communication unit wirelessly communicates with a mobile communication system network. The Web function unit is connected to a content in the mobile communication system network via the wireless communication unit and has a content server function in WWW (World Wide Web). A communication system is also disclosed.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: July 11, 2006
    Assignee: NEC Corporation
    Inventor: Yoshio Nitta
  • Patent number: 7071755
    Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: July 4, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Takanori Saeki
  • Patent number: 7067886
    Abstract: A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: June 27, 2006
    Assignee: International Business Machines Corporation
    Inventors: Henry A. Bonges, III, David L. Harmon, Terence B. Hook, Wing L. Lai
  • Patent number: 7050761
    Abstract: To provide a mobile communication system capable of easily performing selection of an optimal transmission mode. Upon receiving a receiving error notice from a mobile station, a transmission mode switching selecting portion of a base station forwards an instruction to switch a transmission mode to a mode slower than a current transmission mode to a modulation/coding portion. After receiving the receiving error notice, if the receiving error notice is not continuously received for a predetermined number of blocks Ns, the transmission mode switching selecting portion forwards an instruction to switch a transmission mode to a mode faster than the current transmission mode to the modulation/coding portion. The modulation/coding portion switches the modulation/coding code to any one of a QPSK modulation/coding circuit, a 16QAM modulation/coding circuit and a 64QAM modulation/coding circuit in response to the switching instruction and performs modulation/coding in the circuit switched to.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: May 23, 2006
    Assignee: NEC Corporation
    Inventor: Kojiro Hamabe
  • Patent number: 7045829
    Abstract: A Group III nitride compound semiconductor includes a multiple layer structure having an emission layer between an n-type cladding layer and a p-type cladding layer. The n-type cladding layer may be below the emission layer, having been formed on another n-type layer which was formed over a buffer Layer and a sapphire substrate. The emission layer has a thickness which is wider than the diffusion length of holes within the emission layer. The n-type cladding layer is doped with a donor impurity and has a lattice constant Substantially equal to a lattice constant of the emission layer. The p-type cladding layer is doped with an acceptor impurity and has a forbidden band sufficiently wider than the forbidden band of the emission layer in ordor to confine electrons injected into the emission layer.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: May 16, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shinya Asami
  • Patent number: 7034697
    Abstract: An awakening level estimation apparatus for vehicle has: a signal processing part; a frequency component amount calculation part for calculating an average value of the frequency component powers and calculating a maximum value of the frequency component powers; a correction factor calculation part for calculating a high frequency percentile value and calculating a low frequency percentile value and calculating a correction factor; an evaluation value calculation part for calculating an evaluation value; and a decision part for deciding an awakening level of a driver.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: April 25, 2006
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Hajime Oyama
  • Patent number: 7035699
    Abstract: The present invention comprises a system dedicated to computerized information management. In particular, the system is efficiently targeted for employment by industries such as insurance and financial services where it is of interest to effect integrated prospect selection and management. To this end, the present invention can prevent multiple agents from pursuing the same lead at the same time, while collecting data on effectiveness of leads from agents to thereby enhance the quality of prospect information, as well as providing a capability so that an individual agent can tailor particular lead selection preferences.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: April 25, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gary Floyd Anderson, Paul Bao-Luo Chou, David Edward Chzaszcz, Pasumarti Venkata Kamesam
  • Patent number: 7027475
    Abstract: A semiconductor laser device includes a tailored index single mode power amplifier. A high-power laser system can be produced by connecting several of the tailored index single mode power amplifiers in parallel. In an exemplary case, a phase shifting device can be optically coupled to each of the tailored index single mode power amplifiers; the phase shifting devices can be controlled to ensure that the laser beams output by the tailored index single mode power amplifiers are both phase aligned and wavefront matched.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: April 11, 2006
    Assignee: Nuvonyx, Inc.
    Inventors: Mark S. Zediker, Eric E. Bott, Brian O. Faircloth, John M. Haake, James A. Priest
  • Patent number: 7024512
    Abstract: An improved method, system, and a computer program storage device (e.g., including software embodied on a magnetic, electrical, optical, or other storage device) for management of compressed main memory allocation and utilization which can avoid system abends or inefficient operation that would otherwise result. One feature reduces (and ultimately eliminates) all unessential processing as the amount of available storage decreases to a point low enough to threaten a system abend. In another example, the amount of current memory usage is determined as well as one or more of: an estimate of an amount of allocated but unused memory; a determination of the amount of memory required for outstanding I/O requests. The compressed memory is managed as a function of the current memory usage and one or more of the other measured or estimated quantities.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: April 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Philip Heidelberger
  • Patent number: 7016860
    Abstract: An electronic coupon, an electronic commerce system, and a method for the honoring of electronic coupons utilizing computing equipment are disclosed. In the method, an issuing party issues an electronic coupon to a customer. The customer presents the coupon for redemption to a redemption party. The redemption party transmits the coupon to an authentication party for authentication. If authentic, the authentication party charges the redemption party a fee and passes that fee to the issuing party. The redemption party honors the coupon for the customer and seeking reimbursement of the fee from the issuing party. The electronic coupon has a plurality of data fields, including: a coupon identifier, x, a first one-way hash function field, f(x), and a secure signature field.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: March 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Natwar Modani, Parul A. Mittal, Rahul Garg, Alok Aggarwal
  • Patent number: 7016167
    Abstract: A method and structure for a spin valve transistor (SVT) comprises a magnetic field sensor, an insulating layer adjacent the magnetic field sensor, a bias layer adjacent the insulating layer, a non-magnetic layer adjacent the bias layer, and a ferromagnetic layer over the non-magnetic layer, wherein the insulating layer and the non-magnetic layer comprise antiferromagnetic materials. The magnetic field sensor comprises a base region, a collector region adjacent the base region, an emitter region adjacent the base region, and a barrier region located between the base region and the emitter region. The bias layer is between the insulating layer and the non-magnetic layer. The bias layer is magnetic and is at least three times the thickness of the magnetic materials in the base region.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: March 21, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Robert E. Fontana, Jr., Jeffrey S. Lille
  • Patent number: D520525
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: May 9, 2006
    Assignee: TCM Corporation
    Inventors: Yoshiyuki Enmeiji, Yoshiharu Uchida, Takayuki Itou, Yusuke Kamo, Satoshi Horibe
  • Patent number: D520865
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: May 16, 2006
    Assignee: Piolax Inc.
    Inventor: Yasuki Wakabayashi
  • Patent number: D521534
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: May 23, 2006
    Assignee: Janome Sewing Machine Co., Ltd.
    Inventor: Kiyomi Kawaguchi