Patents Represented by Attorney McGinn & Gibb, PLLC
  • Patent number: 6971758
    Abstract: In the illumination device of the invention, an LED is oppose to a side surface of a flat light guide member. A light shield surface for shielding light from the LED and emitted toward the backside of the guide member in vicinity of the LED on the backside of the light guide member.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: December 6, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shuji Inui, Moriyuki Hashimoto, Osamu Yamanaka, Yoshio Sano, Mitsuhiro Nawashiro, Hiroshi Ito, Akihiro Misawa, Takayuki Kamiya
  • Patent number: 6969206
    Abstract: A printing apparatus includes a conveyance mechanism for conveying a web to a transfer unit, and a tension generating mechanism for applying a tension to the web fed to the conveyance mechanism, wherein the tension generating mechanism includes a tension generating roller for changing the tension to be applied to the web in accordance with the rotational position, a tension guide that is rotated in accordance with the magnitude of tension generated by the roller, a first sensor for sensing the rotational position of the tension guide, a second sensor for sensing the rotational position of the tension generating roller, and a driver for controlling the rotation of the motor in accordance with the outputs of the first and second sensors.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: November 29, 2005
    Assignee: Ricoh Printing Systems, Ltd.
    Inventors: Hidenori Iwanaga, Tsukasa Onose, Takeshi Terakado, Yuji Ohmura
  • Patent number: 6970814
    Abstract: A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: November 29, 2005
    Assignee: International Business Machines Corporation
    Inventors: Carl L. Ashley, Charles N. Choukalos, Scott A. Tetreault
  • Patent number: 6970028
    Abstract: DLL circuit with a small minimum delay time while allowing a wide range of adjustment of the delay time. The DLL circuit according includes a first delay circuit for delaying an input clock signal (CLK1) to output a plurality of delayed clock signals (T1 to TN), a first selector (7) for selecting a first delayed clock signal (CLK_E) and a second delayed clock signal (CLK_O) from among the plurality of delayed clock signals (T1 to TN), for output, a second delay circuit (3) for delaying the input clock signal (CLK1) to generate a slightly delayed clock signal (CLKD), a second selector (4) for selecting two selected clock signals (FDLE, FDLO) from among the slightly delayed clock signal (CLKD), first delayed clock signal (CLK_E), and second delayed clock signal (CLK_O), and a delay synthesis circuit (5) for generating an internal clock signal (CLKIN) from the selected clock signals (FDLE, FDLO), for output.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 29, 2005
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Ishikawa
  • Patent number: 6967375
    Abstract: Disclosed in a method of planarizing a silicon on insulator (SOI) structure. The invention performs a first chemical mechanical planarization (CMP) process on an insulator (e.g., oxide) layer. However, this first CMP process creates scratches on the insulator layer. The invention forms a polish stop insulator (e.g., nitride) over the insulator layer in, for example, a liquid phase chemical vapor deposition (LPCVD) process. The polish stop insulator fills in the scratches. The invention then forms an opening through the insulator layer and through the polish stop insulator (e.g., in a reactive ion etching (RIE) process) and deposits a conductor within the opening. The invention performs a second CMP process on the conductor. The polish stop insulator is harder than the insulating layer and prevents the second CMP process from scratching the insulator layer. The invention removes portions of the polish stop insulator to leave the polish stop insulator only within the scratches.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Rainer E. Gehres, George R. Goth
  • Patent number: 6968323
    Abstract: The present invention relates to a computer implementable system and method for allocation and pricing of classified resources of a web server farm to customers by a resource center comprising means for providing different levels of service by dynamically allocating and pricing said resources based on customers' changing needs, and their willingness to pay.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Vipul Bansal, Rahul Garg, Aditya Afzulpurkar, Samrat Sen
  • Patent number: 6967416
    Abstract: A method and structure for an integrated chip structure comprises a substrate having a power supply, a chip attached to the substrate, at least two decoupling capacitors attached to the chip and to the power supply, and a control circuit adapted to select physical locations of active decoupling capacitors to be interspersed with inactive decoupling capacitors. The invention selectively connects and disconnects the decoupling capacitors to and from the power supply, such that the inactive decoupling capacitors provide a uniform heat dissipation function across the chip and the active decoupling capacitors provide a uniform power regulation function across the chip.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Amy R. Hsu, Louis L. Hsu, Kwong Hon Wong
  • Patent number: 6967377
    Abstract: It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Hon-Sum P. Wong
  • Patent number: 6964705
    Abstract: A seed layer as a laminate of a GaN layer (second seed layer) and an AlN buffer layer (first seed layer) is formed on a sapphire substrate. A front surface thereof is etched in the form of stripes with a stripe width (seed width) of about 5 ?m, a wing width of about 15 ?m and a depth of about 0.5 ?m. As a result, mesa portions each shaped like nearly a rectangle in sectional view are formed. Non-etched portions each having the seed multilayer as its flat top portion are arranged at arrangement intervals of L?20 ?m. Part of the sapphire substrate is exposed in trough portions of wings. The ratio S/W of the seed width to the wing width is preferably selected to be in a range of from about ? to about ?. Then, a semiconductor crystal A is grown to obtain a thickness of not smaller than 50 ?m. The semiconductor crystal is separated from the starting substrate to thereby obtain a high-quality single crystal independent of the starting substrate.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: November 15, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Akira Kojima, Kazuyoshi Tomita
  • Patent number: 6964892
    Abstract: An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Rama Divakaruni, Louis Lu-Chen Hsu, Yujun Li
  • Patent number: 6965627
    Abstract: Fiber gratings (5), (6) having substantially the same reflection center wavelength are provided in an optical fiber (4). The fiber gratings (5), (6) reflects to the semiconductor laser element (1), only a component at the reflection center wavelength of laser light emitted from the semiconductor laser element (1).
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: November 15, 2005
    Assignee: NEC Corporation
    Inventors: Masahiko Namiwaka, Masahiro Kanda
  • Patent number: 6965884
    Abstract: By employing easy determination logic, the amount of communication required for broadcasting and relaying is effectively reduced, and the message transmission efficiency is improved. A mobile terminal T2 includes determination logic. According to this logic, when a message is issued, via an arbitrary terminal, by a transmission source terminal T0 to a relay terminal T1, and the message is relayed by the relay terminal T1 to the terminal T2, the terminal T2 calculates an information progress vector I, which indicates the direction in which information progresses, and a terminal progress vector M, which indicates the direction in which the terminal T2 progresses. Then, the terminal T2 obtains an inner product cos ? for which the information progress vector I and the terminal progress vector M are standardized, and forwards the received message when the condition cos ??0 is established.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Yasuharu Katsuno, Ryoji Honda
  • Patent number: 6964527
    Abstract: The present invention provides a substrate, an optical fiber connecting end member, an optical element-housing member, a light module, and a manufacturing method of the substrate. The substrate has a feature that can be stably realizable and having a simple structure and that a light waveguide formed on the substrate surface or an optical element formed thereon can be connected without core alignment to an optical element provided on the optical fiber of the optical fiber connector to be connected to the optical fiber connecting end member. The substrate of the present invention is characterized in steps 5 for positioning being formed on at least one side of the substrate 1 that provides the optical waveguide 4.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: November 15, 2005
    Assignee: NEC Corporation
    Inventors: Junichi Sasaki, Kazuhiko Kurata, Takanori Shimizu
  • Patent number: 6965126
    Abstract: In a light-emitting element in which an n-type layer of a Group III nitride compound semiconductor, a light-emitting layer of a Group III nitride compound semiconductor and a p-type layer of a Group III nitride compound semiconductor are laminated successively on a substrate, a semiconductor layer of ZnxCd1?xSySe1?y (0?x?1, 0?y?1) which receives a part of blue light from the light-emitting layer to thereby emit yellow light, is interposed between the n-type Group III nitride compound semiconductor layer and the light-emitting layer.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: November 15, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Tetsuya Taki
  • Patent number: 6962828
    Abstract: A novel light-emitting device includes a saphire substrate with a light-emitting layer comprising InXGa1?XN, where the critical value of the indium mole fraction X is determined by a newly derived relationship between the indium mole fraction X and the wavelength ? of emitted light.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: November 8, 2005
    Assignees: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Masayoshi Koike, Shiro Yamasaki, Isamu Akasaki, Hiroshi Amano
  • Patent number: 6962398
    Abstract: A method of driving an ink jet recording head, and an ink jet recording apparatus. A driving wave form for driving a piezoelectric actuator includes a first voltage changing process to compress a pressure generating chamber with a rise time of t1, and a second voltage changing process to expand the pressure generating chamber with a fall time of t3 after the voltage is maintained during a time of t2. The start time, the voltage changing time, and the voltage variation of the second voltage changing process are set so that, in a room temperature environment, a first peak value v1 and a second peak value v1 of particle velocity generated at the nozzle section satisfy the condition: 0.3?v2/v1?0.6.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: November 8, 2005
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Masakazu Okuda, Tomohiro Wada
  • Patent number: 6963032
    Abstract: A foamed coaxial cable with high precision according to the present invention comprises: an internal conductor twisted with a plurality of electrically conductive wires; a foamed insulator with its low dielectric constant made of a porous tape body formed on the outer periphery of this internal conductor; an external conductor made of a number of electrically conductive thin wires braided on the outer periphery of this foamed insulator; and an outer sheath made of a resin having heat resistance formed on the outer periphery of this external insulator, wherein the precision of external diameter of the internal conductor is 4/1000 mm or less, the precision of external diameter size of the foamed insulator is ±0.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: November 8, 2005
    Assignees: Hirakawa Hewtech Corporation, Advantest Corporation
    Inventors: Tetsuo Yamaguchi, Mitsuo Iwasaki, Takao Ishido, Takaaki Kusama, Mitsuo Nanjyo, Shigeru Matsumura, Shigeru Murayama
  • Patent number: 6963534
    Abstract: The present invention relates to a computer implemented system for transferring data over a master driven TDD/TDMA based wireless network operating with minimum delay in end-to-end transmission by achieving optimum time slot utilization by minimizing the number of baseband packets created for each Link layer packet, where each baseband packet of is a size corresponding to one of a permitted set of capacities ‘C1, C2, . . . Cn’. The system also optimizes sharing of bandwidth, higher link utilization and low baseband packet transmission queue occupancy by adaptive scheduling of the transmission of the baseband packets in the queues. The invention also provides a method and computer program product for the above system.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: November 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Rajeev Shorey, Ashu Razdan, Abhishek Das, Abhishek Ghose, Huzur Saran
  • Patent number: 6962685
    Abstract: A method and structure for making magnetite nanoparticle materials by mixing iron salt with alcohol, carboxylic acid and amine in an organic solvent and heating the mixture to 200–360 C is described. The size of the particles can be controlled either by changing the iron salt to acid/amine ratio or by coating small nanoparticles with more iron oxide. Magnetite nanoparticles in the size ranging from 2 nm to 20 nm with a narrow size distribution are obtained with the invention. The invention can be readily extended to other iron oxide based nanoparticle materials, including M Fe2O4 (M=Co, Ni, Cu, Zn, Cr, Ti, Ba, Mg) nanomaterials, and iron oxide coated nanoparticle materials. The invention also leads to the synthesis of iron sulfide based nanoparticle materials by replacing alcohol with thiol in the reaction mixture.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: November 8, 2005
    Assignee: International Business Machines Corporation
    Inventor: Shouheng Sun
  • Patent number: D512251
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: December 6, 2005
    Assignees: Itoki Co., Ltd., Itoki Crebio Corporation
    Inventors: Tamio Sakurai, Koichiro Hayashi