Patents Represented by Attorney McGinn IP Law Group
  • Patent number: 8313241
    Abstract: A magnetic encoder is provided which can prevent a magnetized member from being separated from a fixed member to which the magnetized member is fixed under a severe temperature environment. The encoder includes a fixed member which is fixed to a rotating member and a magnetized member which is attached to the fixed member. The magnetized member, which is molded by mixing a magnetic powder in a resin, is bonded to the fixed member with a silicone resin based adhesive, and a thickness of an adhesive layer of the silicone resin based adhesive is 50 ?m or more and 100 ?m or less.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: November 20, 2012
    Assignees: JTEKT Corporation, Nakanishi Metal Works Co., Ltd.
    Inventors: Yasuhiko Ishii, Naoki Morimura, Yoshihiro Itoh, Takashi Kaneike
  • Patent number: 8314638
    Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiro Nakahara
  • Patent number: 8312071
    Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Krishnan Kunjunny Kailas, Brian Chan Monwai, Viresh Paruthi
  • Patent number: 8310966
    Abstract: By more flexibly controlling connection for each transmission rate in the wireless base station, the connection is established using possibly a higher transmission rate so long as the connection capacity of the wireless base station has a margin while efficiently determining the transmission rate according to the wave intensity from a wireless communication terminal. If the connection capacity of the base station has a margin after additionally connecting one wireless communication terminal, i.e., if the communication traffic is equal to or less than a predetermined margin threshold value, the rate decision threshold value to determine the transmission rate for connection is lowered by a predetermined value to determine a transmission rate so that the connection is established using a transmission rate higher than that determined by the rate decision threshold value as the default value (initial value) to thereafter establish the connection.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: November 13, 2012
    Assignee: NEC Infrontia Corporation
    Inventor: Ryuichi Toshida
  • Patent number: 8311502
    Abstract: A communication device includes a transmission signal processing unit, a driver amplifier coupled to the transmission signal processing unit, a selector coupled to the driver amplifier, a first attenuator coupled to the selector and an output portion of the communication device, a second attenuator coupled to the selector and the output portion of the communication device, and a controller coupled to the selector and the driver amplifier to switch between the first attenuator and the second attenuator based on a notification signal.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Junjirou Yamakawa
  • Patent number: 8310430
    Abstract: A driver includes a plurality of output portions; and an output switching control portion. The plurality of output portions is synchronized with a shift pulse signal. The shift pulse signal indicates one specification shift pulse signal among a plurality of specification shift pulse signals. The plurality of specification shift pulse signals indicates a plurality of output numbers which are different from each other based on respective specifications of the plurality of specification shift pulse signals. The one specification shift pulse signal indicates a setting output number as one output number among the plurality of output numbers. The output switching control portion selects a group of output portions corresponding to the setting output number among the plurality of output portions based on the one specification shift pulse signal.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Hiratsuka
  • Patent number: 8310431
    Abstract: A format of an inputted video signal is estimated to be based on the total number of vertical lines, and a frequency dividing ratio of a PLL unit is provisionally set at a predetermined value corresponding to the estimated format. Next, the frequency dividing ratio is calculated so that a measured value of a horizontal display width that is measured by a video detecting unit matches a capture width which is the horizontal display width capturable by a frame memory, and the calculated frequency dividing ratio is converted to a multiple of 4. A phase adjustment of the regenerative dot clock is performed against the video signal based on the converted frequency dividing ratio by using the regenerative dot clock generated by the PLL unit.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: November 13, 2012
    Assignee: NEC Display Solutions, Ltd.
    Inventor: Tatsuo Kimura
  • Patent number: 8308453
    Abstract: A pump chamber (15) is formed between a piezoelectric vibrator (7) and a valve main plate (10). The valve main plate (10) includes an inlet port (13) at its central portion, and an outlet port (14) in its peripheral portion, and the inlet port (13) is made in a smaller diameter than the outlet port (14). On the valve main plate (10) an inflow check valve (11) and an outflow check valve (12) are provided, so that when the inflow check valve (11) and the outflow check valve (12) open and close in response to the vibration of the piezoelectric vibrator (7), a fluid is introduced into and discharged from the pump chamber (15).
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: November 13, 2012
    Assignee: NEC Corporation
    Inventors: Mitsuru Yamamoto, Kazuhito Murata, Sakae Kitajo
  • Patent number: 8310297
    Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenjyu Shimogawa, Hiroshi Furuta
  • Patent number: 8310589
    Abstract: Disclosed is a digital still camera in which amount of exposure is decided appropriately even when there is a changeover from one shooting scene to another. When a shooting mode is set, a first shooting scene discrimination is performed before a shutter-release button is half-pushed. A first amount of exposure is calculated using a program diagram suited to the shooting scene that has been discriminated by the first shooting scene discrimination. Shooting for focusing control is performed at an exposure corresponding to the first amount of exposure, whereby image data is obtained. Focusing control is carried out based upon the image data obtained, and shooting is performed again. Second shooting scene discrimination is performed based upon the image data obtained by shooting. A second amount of exposure is calculated using a program diagram suited to the shooting scene that has been discriminated by the second shooting scene discrimination.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: November 13, 2012
    Assignee: Fujifilm Corporation
    Inventor: Satoshi Okamoto
  • Patent number: 8310049
    Abstract: A semiconductor device includes a semiconductor chip having a current path between a first principal surface and a second principal surface opposite from the first principal surface, a first conductive frame having an opposite region to the first principal surface, and a second conductive frame electrically connected via electrical connection member to a pad formed on the second principal surface. In a gap between the first principal surface and the first conductive frame, there are arranged multiple column-shaped lead-free solders which are arranged within a circle drawn around a center of the opposite region and having a diameter corresponding to a narrow side of the opposite region, and which electrically connects the first conductive frame with the semiconductor chip, and a filler which is filled between the multiple column-shaped lead-free solders.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hideko Andou
  • Patent number: 8308610
    Abstract: A device for controlling a power transmission device for a vehicle, which, at the time of gearshift, so controls the engine as to rotate at a target rotational speed, wherein at the time of shifting the gear up, a target value properly corresponding to an actual vehicle speed is set to quickly increase the engine output and to shorten the time for shifting the gear. In controlling the engine at the time of shifting the gear up, a target engine rotational speed is set based the signals from, wheel rotational speed detector means that detects the rotational speed of a wheel, such as an anti-lock control device. Thus, the target engine rotational speed is set depending properly upon an actual vehicle speed that varies accompanying an increase in the amount of engaging the clutch at the time of gearshift, and the gear at the time of accelerating the vehicle can be quickly shifted up without accompanied by the shift shock.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: November 13, 2012
    Assignee: Isuzu Motors Limited
    Inventors: Nobuyuki Iwao, Hiroshi Usuba
  • Patent number: 8312403
    Abstract: A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuyuki Irie
  • Patent number: 8310917
    Abstract: A switching hub for processing a VLAN frame transmitted through a transmission line of a ring network includes two ring ports connected to the transmission line of the ring network, and a forwarding processing mechanism for, when one of the two ring ports receives the frame and when a VLAN in which the received frame belongs is a VLAN only through both the ring ports, forwarding the frame to the other ring port without performing FDB learning on the frame.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: November 13, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Koichiro Seto, Kenji Aoshima
  • Patent number: 8308503
    Abstract: A flat cable includes a plurality of conductors arranged in parallel and exposed at both end portions in a longitudinal direction thereof, an insulation film covering the plurality of conductors except the exposed both end portions, and a reinforcing member that covers the plurality of conductors along a width direction of the plurality of conductors, is provided on a surface of the insulation film in a part of a region including an edge of the insulation film, and includes a metal plate and an insulative covering layer for covering the metal plate.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akihiro Yaguchi, Takumi Kobayashi, Kenichi Murakami, Hiroaki Komatsu
  • Patent number: 8307968
    Abstract: This invention provides a one-way clutch capable of hindering the generation of a coating between each sprag and each of inner and outer rings thereby preventing sprags and inner and outer rings from being damaged due to the slip therebetween and thereby lengthening the life of the engagement between each sprag and each of the inner and outer rings. The difference in surface hardness between each sprag (4) and each of an inner ring (2) and an outer ring (3) is set to be larger than a hardness of Rockwell C-scale HRC0 and to be equal to or smaller than HRC15.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: November 13, 2012
    Assignee: JTEKT Corporation
    Inventor: Shinji Yamane
  • Patent number: 8310422
    Abstract: An operational amplifier circuit includes: an input differential stage circuit supplied with power supply voltages in a first voltage range; and an output stage circuit supplied with power supply voltages in a second voltage range which is different from the first voltage range. The operational amplifier circuit amplifies a signal supplied to the input differential stage circuit and outputs the amplified signal from the output stage circuit to drive a load.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Nishimura
  • Patent number: 8311362
    Abstract: Sharpness is calculated in all of focus-bracketed images on a pixel basis. Then, a first reference value indicating an image of the plurality of images to which a pixel whose sharpness is the highest among the pixels located on the identical positions in the plurality of images belongs is obtained on each pixel of the images, and a second reference value is calculated based on the first reference value on each pixel by spatially smoothing the first reference value on each pixel based on the first reference values on adjacent pixels. The focus-bracketed images are processed based on the second reference values to generate an omni-focus image or a blur-enhanced image. Accordingly, it is possible to judge a region having high contrast as an in-focus region and acquire a synthesized image having smooth gradation.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: November 13, 2012
    Assignee: Fujifilm Corporation
    Inventor: Masaya Tamaru
  • Patent number: 8312238
    Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: November 13, 2012
    Assignee: RENESAS Electronics Corporation
    Inventors: Rika Ono, Hitoshi Suzuki
  • Patent number: 8310889
    Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiro Banno