Patents Represented by Attorney McGinn IP Law Group
  • Patent number: 8309859
    Abstract: A substrate includes a base material, a first solder part disposed on a surface of the base material and used for connection to an electronic component, and a second solder part disposed on the surface of the base material and made of the same solder as that of the first solder part. The top surface of the first solder part is made to be a flat surface, and the maximum height of the second solder part from the surface of the base material is lower than the height of the flat surface of the first solder part from the surface of the base material. Thus, a substrate for which the kind of solder can be determined easily and with certainty, a device provided with this substrate, a method of manufacturing the substrate, and a determining method are provided.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Chiho Ogihara
  • Patent number: 8308373
    Abstract: An outer tapered member (4) having a conical inner circumferential surface is placed and an inner tapered member (5) having a conical outer circumferential surface in contact with the conical inner circumferential surface is placed in a through hole (31) of a first ring (1). A screw member (6) is screwed a predetermined quantity into the through hole (31) to axially press an axial end face of the inner tapered member (5) toward a second ring (2) with a predetermined force and to press the outer surface of the outer tapered member (4) against the through hole (31) of the first ring (1) with a predetermined force. A weld part (7) in contact with a first ring (1) side end portion of a pin (3) and the first ring (1) is formed to prevent the pin (3) from coming out of the first ring (1) by the weld part (7).
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: November 13, 2012
    Assignee: JTEKT Corporation
    Inventors: Takeshi Miyachi, Junichi Kubo
  • Patent number: 8310382
    Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Akira Ide, Ryuji Takishita
  • Patent number: 8310035
    Abstract: Even when only one of semiconductor packages mounted by carrying out infrared reflow is defective, it is required to carry out infrared reflow again to dismount this defective semiconductor package from a mounting board. At this time, stress of heat is also applied to the other non-defective semiconductor packages. For this reason, if infrared reflow is carried out beyond a number of times of infrared reflow specified for non-defective semiconductor packages, the operation of each non-defective semiconductor package cannot be assured. In this case, it is inevitable to discard the semiconductor packages together with the mounting board. To solve this problem, a magnetic material is passed through a hole penetrating a protection member and a package board and the relevant semiconductor package is fixed over a mounting board by this magnetic material. To supply power to the semiconductor package, electromagnetic induction by coils provided in the package board and the mounting board is used.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kou Sasaki
  • Patent number: 8308370
    Abstract: In a sealing device for a bearing, a sub-seal lip is configured such that a slide contact surface is formed like an annular band. As the rotation speed of the bearing increases, the width of the slide contact surface is reduced by a centrifugal force. Thus, sliding friction can effectively be minimized. The torque of the bearing can be prevented from increasing at high-speed rotation. Even when the centrifugal force increases somewhat, only reduction in the width of the slide contact surface is caused. Thus, a slide-contacted state can be maintained. Consequently, the problem of floating-up of the sub-seal lip from a slinger is difficult to occur.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: November 13, 2012
    Assignee: JTEKT Corporation
    Inventors: Yoshitaka Nakagawa, Youichi Numada, Hajime Tadumi, Tsuyoshi Okumura, Kunihiro Yamaguchi, Ikuo Ito
  • Patent number: 8312333
    Abstract: An operation terminal, which includes an operation terminal, when connected to a group administration apparatus for administering a plurality of substrate processing apparatuses for processing substrates, generates a data acquisition request format that sets forth retrieval conditions and types of display items classified in individual tables for the substrate processing apparatuses, and then transmits it to the group administration apparatus.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Toshiro Koshimaki
  • Patent number: 8310507
    Abstract: Provided is a display device drive circuit capable of setting an optimum drive performance for each output amplifier without increasing the chip size. The display device drive circuit includes: at least two bias lines having different reference potentials; a selector that selects one of the bias lines based on a grayscale signal; and an output amplifier that is supplied with a reference potential of the one of the bias lines selected by the selector, generates a display signal, and supplies the display signal to a data line.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Hiratsuka
  • Patent number: 8310056
    Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriaki Oda, Shinichi Chikaki
  • Patent number: 8310068
    Abstract: A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Suguru Sasaki
  • Patent number: 8310425
    Abstract: A resistance dividing circuit includes a resistive element formed in an area in a first line segment and a second line segment which are set on a substrate and arranged in parallel to each other; and a tap portion connected to the resistive element at a predetermined position of the first line side. A cutout in which the resistive element does not exist is formed in a place corresponding to the predetermined position in a lengthwise direction of the resistive element. In such a structure, a deviation of an actually generated divided voltage from a design value thereof can be reduced so that a highly correct gray-scale display can be achieved.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Okutani, Masaharu Takahashi
  • Patent number: 8312408
    Abstract: A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Daishin Itagaki
  • Patent number: 8310426
    Abstract: A liquid crystal display device is provided with a liquid crystal display panel, and a data driver IC that drives the liquid crystal display panel. The liquid crystal display panel is provided with a gate line, first and second data lines, and a pixel that includes a first sub-pixel connected to the gate line and the first data line and a second sub-pixel connected to the gate line and the second data line. The data driver IC is provided with a gamma correction circuitry and a drive circuitry. The gamma correction circuitry generates first gamma-corrected data by performing gamma correction on externally received image data in accordance with a first gamma curve, and generates second gamma-corrected data by performing gamma correction on the image data in accordance with a second gamma curve. The drive circuitry drives the first data line in response to the first gamma-corrected data and drives the second data line in response to the second gamma-corrected data.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kengo Umeda
  • Patent number: 8308510
    Abstract: A wire harness includes a cable, a connector including an outer housing including a resin, a cable insertion hole into which an end portion of the cable is inserted, and a concave portion formed on an insertion side of the cable insertion hole, and a welding member including a resin to provide air-tightness between the outer housing and the cable by being welded to the outer housing by ultrasonic welding. The welding member is formed around the cable so as to surround the cable while allowing a gap portion to have a predetermined clearance from the cable, and fitted into the concave portion of the outer housing. Melted resin of the welding member is to flow into the gap portion to form an airtight seal about the cable.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 13, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Sachio Suzuki, Hideaki Takehara, Kunihiro Fukuda, Yuta Kataoka
  • Patent number: 8310887
    Abstract: A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a control electrode thereof to the bit line, a second transistor coupled to the bit line and supplied at a control electrode thereof with a first control signal, a global bit line, and a third transistor coupled in series with the first sistor between a node and the global bit line, the third transistor supplied at a control electrode thereof with a second control signal.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8307561
    Abstract: There is provided a jig for measuring a runout of a flange surface of a hub unit adapted to be fitted between a plurality of plate-shaped projecting portions of a road wheel mounting flange of a deformed type including the plurality of plate-shaped projecting portions. The projecting portions are formed on an outer circumferential surface of a hub wheel serving as a rotating side member of a road wheel hub unit so as to project radially. Each of the projecting portions has a bolt insertion hole in a distal end portion thereof. The jig is positioned adjacent to a flange surface of the projecting portions so as to form an annular continuous surface.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: November 13, 2012
    Assignee: JTEKT Corporation
    Inventors: Shigeru Inoue, Keiichiro Isoda, Tsutomu Senoo
  • Patent number: 8311273
    Abstract: An object detecting apparatus and method includes a pixel state determining unit that derives variance value for temporal properties of pixel characteristics of an input image, background model generating unit that adaptively generates a background model from characteristics in the characteristic storing unit and characteristic storing unit for background model generation using the characteristic distance and the pixel state determined as conditions, and an object judging unit that judges an object based on a characteristic distance indicative of a degree of similarity between a generated background model and pixel characteristics of an input image.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: November 13, 2012
    Assignee: NEC Corporation
    Inventor: Hiroo Ikeda
  • Patent number: 8310034
    Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 13, 2012
    Assignee: RENESAS Electronics Corporation
    Inventors: Shinichi Uchida, Takasuke Hashimoto, Masayuki Furumiya, Kimio Hosoki, Hideo Ohba
  • Patent number: 8310220
    Abstract: A power supply controller includes an analog to digital (A/D) converter that performs analog-digital conversion of an output voltage and outputs a digital signal, a deviation signal generator unit that generates a deviation signal from the digital signal and a standard voltage value serving as an output voltage target value, and a power controller unit that controls the output voltage based on the deviation signal. The power supply controller includes a conversion range setting unit that sets a range of the reference voltage into the A/D converter based on a first signal as the digital signal in a power supply startup period, and sets the reference voltage range into the A/D converter based on a second signal as the deviation signal or as a signal corresponding to the deviation signal in a steady state period.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hideyuki Takahashi, Yoshimi Matsumoto
  • Patent number: 8308591
    Abstract: A resin pulley includes an outer cylindrical portion including an outer circumferential surface on which a belt is to be wound, an inner cylindrical portion, and a plurality of ribs connecting an inner circumferential surface of the outer cylindrical portion and an outer circumferential surface of the inner cylindrical portion, which are formed of a resin material. The ribs are provided so as to be inclined towards a circumferential direction relative to a radial imaginary line as viewed in an axial direction. Radially outer end portions of the ribs are formed such that inclination angles of the respective radially outer end portions relative to the radial imaginary line increase as the ribs extend radially outward, and radially inner end portions of the ribs are formed such that inclination angles of the respective radially inner end portions relative to the radial imaginary line increase as the ribs extend radially inward.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 13, 2012
    Assignee: JTEKT Corporation
    Inventors: Kazuki Hamada, Hiroshi Ueno, Kunio Yanai, Masanori Shinohara, Tomoki Uno
  • Patent number: 8310125
    Abstract: In a motor comprising a stator and a rotor disposed in an inner circumference of the stator, the stator comprises a substantially cylindrical stator core and coils made up of wound conductors, and the stator core comprises an outer circumferential portion which constitutes an outer circumferential wall of the stator and an inner circumferential portion round which the conductors are wound. The outer circumferential portion is formed of a first sintered metal made of a powder magnetic material, while the inner circumferential portion is formed of a second sintered metal made of a powder magnetic material, and the first sintered metal is a sintered metal having a higher mechanical strength than the second sintered metal. Additionally, the stator core is formed by diffusion bonding the outer circumferential portion and the inner circumferential portion being bonded together.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: November 13, 2012
    Assignee: JTEKT Corporation
    Inventor: Yasuhiro Yukitake