Abstract: A method for parsing for natural languages includes a grammar and a lexicon. A knowledge base may be used to define elements in the lexicon. A processor receives single words input by a user and adds them to a sentence under construction. Valid next words are predicted after each received input word. The preferred system has two major components: a parser and a predictor. The predictor accesses only the lexicon and the knowledge base, if one is used, to determine the valid next input words. The parser constructs sentences which are valid according to the grammar out of words accepted by the predictor.

Abstract: An on-chip power supply regulation system for a VLSI circuit such as a dynamic RAM is disclosed. The system includes a high power supply voltage detection circuit and a power supply clamp circuit, where a clamped voltage generated by the clamp circuit biases the functional circuitry when the high power supply voltage detection circuit detects an overvoltage conditions. The bias voltage applied to the functional circuitry in the normal operating condition can be a regulated voltage generated from the power supply voltage. Further included in the disclosed circuit is a burn-in voltage generation circuit and a burn-in voltage detection circuit, which can apply an accelerated voltage which depends upon the applied power supply voltage, when the power supply voltage is higher than during normal operation but lower than in the overvoltage condition enabling the clamp operation.

Abstract: Thyristors of one conductivity type formed as an array in a first semiconductor body are respectively connected in parallel with thyristors of the opposite conductivity type formed as an array in a second semiconductor body to produce an array of triacs. In each body the thyristors are separate except for a common anode or cathode region and terminal connection, and are formed in an epitaxial layer divided by PN junction isolation regions on a substrate of opposite conductivity type. The thyristors may be constructed to be triggered by gating signals of either polarity.

Abstract: A damping circuit is described for the antenna resonance circuit (28) of a radio transmitter-receiver (10) which in a transmitting phase transmits a time-limited high-energy interrogation pulse and in a receiving phase following the transmitting phase is ready to receive high-frequency response signals coming from a responder (26) which transmits said response signals as reaction to the reception of the interrogation pulse. In the damping circuit (24) a damping member (R5, R5, R6) is provided which is adapted to be connected to the antenna resonance circuit and disconnected therefrom. A switching means (T4, T5) on receiving a switching voltage applies the damping member (R4, R5, R6) to the antenna resonance circuit (28).

Abstract: A uniphase, buried-channel, semiconductor charge transfer device wherein a portion of each cell includes an inversion layer, or "virtual electrode" at the semiconductor surface, shielding that region from any gate-induced change in potential. Each cell is comprised of four regions (I, II, III, IV) wherein the characteristic impurity profile of each region determines the maximum potential generated therein for the gate "on" and gate "off" conditions. Clocking the gate causes the potential maxima in regions I and II to cycle above and below the fixed potential maxima in regions III and IV beneath the virtual electrode. Directionality of charge transfer is thereby achieved, since the potential maximum for region II (.phi..sub.max II) remains greater than for region I (.phi..sub.max I) and .phi..sub.max IV>.phi..sub.max III, for both gate conditions.

Abstract: A CCD imager cell (36, 38) is formed at a face of a semiconductor substrate (10) and has first (36) and second (38) phase regions. A first clocked well (14) is provided for receiving charge integrated in the first phase region (36). A second clocked well (16) is provided for receiving charge integrated in a second phase region (38) adjacent the first phase region (36). A first gate (20) is insulatively disposed over the first clocked well (14), and a second gate (22) is insulatively disposed over the second clocked well (16). A controller controls .phi..sub.1 and .phi..sub.2 pulses such that the charge is transferred from a selected one of the first and second clocked wells (14, 16) to the other, thus integrating all of the charge in the cell into one clocked well thereof. This unified charge is then transferred out from clocked well to clocked well.

Abstract: A cost-effective word recognizer. Each frame of spoken input is compared to a set of reference frames. The comparison is equivalent to embodying the reference frame as an LPC inverse filter, and is preferably done in the autocorrelation domain. To avoid the instability and computational difficulties which can be caused by a high-gain LPC inverse filter, a noise floor is introduced into each reference frame sample. Thus, for each input speech frame, a scalar measures its similarity to each of the vocabulary of reference frames.To achieve connected word recognition based on this similarity measurement, a dynamic programming algorithm is used in which time warping to match a sample to a reference is in effect permitted, and in which matching is performed with unconstrained endpoints.

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO.sub.2 hard mask. The SiO.sub.2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiO.sub.x (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: Electron beam apparatus for use in testing integrated circuits uses a magnetic electron objective lens having a first end adjacent the circuit under test and a second end remote from the circuit. The magnetic field of the lens increases steeply to a maximum near the first end and falls gradually towards the second end. Secondary electrons emitted from the circuit are accelerated strongly by an electrostatic field into the first end of the lens and are retarded abruptly to speeds of the same order as their emission speeds in the region of maximum magnetic field. Further gradual retardation of the electrons takes place so that the electrons approach the second end of the lens parallel to the axis of the lens at substantially their emission speeds. A filter grid located at the second end of the lens and a collector of electrons passing through the filter grid enable the emission speeds of the secondary electrons to be measured.

Abstract: A substrate for mounting a flip-chip on a metallized circuit on the upper surface of the substrate. The substrate is silicon carbide condensed on a graphite or silicon core. The upper surface of the silicon carbide has a layer of insulating material comprised of silicon oxide, silicon nitride, aluminum nitride, boron nitride, an organic insulator such as polyimide, and diamond. The insulator prevents inadvertent shorting of the integrated circuit. The insulating layer can be deposited on the silicon carbide by such processes as chemical vapor deposition, sputtering, spinning or roller coating.

Abstract: A procedure in the formation of semiconductor devices for depositing TiN wherein silane and preferably SiH4 is substituted for the hydrogen in the prior art procedures to provide the approximate twofold to fivefold increase in TiN deposition rate at 400 degrees C. It is believed that the reason for the deposition rate increase is that there is a larger free energy change in the reaction which is believed to occur according to the equation: TiCl4+SiH4+NH3.fwdarw.TiN+SiCl4+(7/2)H2. The above described reaction provides cleaner films when performed in a cold wall CVD reactor than is provided by the prior art procedures as described above. Resistivity of 100 microohm-cm has been measured, this being typical of sputtered TiN films.

Abstract: The described embodiment of the present invention utilizes the regular nature of a large number of arrays by providing a grid scheme in the array to provide a low impedance point to point interconnection. In the described embodiment of the present invention a DRAM includes a number of leads running perpendicular to the sense amplifier layout. For a given signal, each lead is interconnected at a bus lead running parallel to the layout of the sense amplifiers. Thus each lead in the parallel array carries a portion of the current. In addition, in this scheme it can be assured that a substantial number of leads will be near any particular sense amplifier which is drawing on the signal provided on the grid array scheme. Because of the close proximity of the parallel conductors, the bus lines to the sense amplifiers need not be as wide as feeder lines in the prior art.

Abstract: A temperature compensation circuit (FIG. 5a) has a controlled temperature compensated voltage drop across R1. A Schottky diode D1 is connected to the base of Q1 through resistor R1. The temperature coefficients of the base-emitter junction of Q1 and the diode D1 have a predetermined differential, preferably none. The forward voltage drop across D1 and the base-emitter junction are different, thereby establishing a controlled current through resistor R1 that is independent of temperature.

Abstract: A semiconductor circuit apparatus including several semiconductor substrates interconnected by having elevated portions of one substrate contacting the surface of the second substrate where both substrates include at least one electrical circuit. Also included is a method for forming this three dimensional integrated circuit structure by forming the elevated portions of the semiconductor substrate by applying an orientation-dependent etch and then applying an electrically conductive coating to this elevated portion. Electrically conductive bonding pads are formed on the second semiconductor substrate. These pads are selectively positioned relative to the elevated portions formed on the first semiconductor substrate. Contacts between the first and second substrate are formed by forming bonds between the elevated portions on the one substrate and the electrically conductive pads on the second substrate.

Abstract: A semiconductor memory device is constructed so that a plurality of word lines may be simultaneously selected by the transfer of information through a plurality of shift register positions of a shift register, wherein the respective shift register positions are connected to individual word lines. Simultaneously with the selection of the word lines, data may be written in or readout from the memory. The shift register is part of an address decoder which also includes logic circuits providing first and second selector devices. The first selector device is connected between a control circuit and the initial shift register position, while the second selector device is connected between the control circuit and each of the plurality of shift register positions arranged in parallel. When the first selector device is activated by a first control signal from the control circuit, binary data is clocked through each of the shift register positions.

Abstract: Calculating machine comprising a microprocessor (1) controlling the operations carried out by the machine, a stack (2) of shift registers connected to the microprocessor and intended for the temporary storage of the numbers with which the operations are to be carried out, a read only memory (ROM) (7) containing the programs relating to the functions of the machine, a display controller (5) connected to the microprocessor (1) and to the ROM (7) and a screen (10) for displaying results, characterized in that it furthermore has means for displaying on the display screen (10) of the machine educational information relating to the mathematical rules governing the operation carried out by the machine.

Abstract: An electronic handheld arithmetic learning aid which includes a speech synthesis device, a speaker driven by the speech synthesis device, a memory having digital data stored therein from which a plurality of mathematical problems may be derived for presentation to an operator for solution, and a controller for accessing selected portions of the digital data from the memory for input to the speech synthesizer device in presenting the mathematical problems to the operator in an audibly voiced manner via the speaker. In one aspect, at least some of the mathematical problems derivable from the memory involve respective sets of at least two individual numbers from which the operator is expected to determine a particular mathematical relation in providing a solution to the corresponding mathematical problem.

Abstract: An echo effect is synthesized in a coded digital sound signal. An input sound signal is stored as a plurality of sequential frames of similar duration, each frame (n) having characteristics including an energy (E). A delay period (d) is selected as equal to a number of time. For each frame (n) later than the duration of frames of the delay (d), the energy E(n) of the frame is compared to an attenuated energy aE(n-d) of an earlier frame (n-d), which is earlier in time than frame (n) by a number of frames equal to the delay (d). If the energy E(n) is less than the attenuated energy aE(n-d) of the earlier frame, the current frame is replaced in an output sequence with a new frame having the non-energy characteristics of the earlier frame and the attenuated energy.

Abstract: A data communication system in which a host data processing system is responsive to an automated sequence of data processing request signals from a remote data processing system. The remote data processing system includes a means for generating and storing in a nonvolatile read/write memory a log on signal which initiates the communications and causes the host system to be responsive to the remote system, a plurality of data processing request signals specifying operations to be performed by the host system and a log off signal for terminating the data communications. Special data processing request signals may include a predetermined delay before transmission of the next data processing request signal by the remote system or may require the host system to transmit a predetermined response signal in order to enable continuation of the sequence of data processing request signals from the remote system.

Abstract: A method of employing a semiconductor memory system in the storage and readout of video signal data, wherein first and second FIFO memories are utilized in a tandem manner to perform video-related operations in a plurality of functional modes, such as a flicker free mode, picture-in-picture mode, teletext mode, multi-picture mode, stroboscopic mode and still picture mode.