Abstract: The present invention provides a conversion between a speech mode in which each word is clearly enunciated as if spoken in isolation and in which a phrase is spoken as a whole taking into account the influence of adjacent words. In the phrase mode, word ending final phonological linguistic units are replaced with their corresponding internal versions, and short strong vowels are substituted for the corresponding long strong vowels except at the word ends. In the word mode, a word final pronunciation is given when a corresponding internal phonological linguistic unit occurs at a word end, and short strong vowels are replaced by the corresponding long strong vowel when the short strong vowel occurs at the end of a word or prior to a set of voiced consonants. In either mode, a substitution may be made for the pronunciation of frequently used words. This invention is most useful in speaking electronic learning aids which permit word or phrase speech synthesis from the same data.

Abstract: A micropackage for providing high density, three dimensional packaging of integrated circuit chips. A chipmount (10) includes a plurality of channels (36) on the bottom surface thereof for holding a corresponding plurality of integrated circuit chips (16). A shallow cavity (34) is formed on the top surface of the chipmount (10) for holding another integrated circuit (14). Metallization interconnections (22) are formed on the top and bottom surfaces of the chipmount (10) and are terminated by solder pads (24, 39). Conductive conduits (26) are formed through the chipmount (10) for providing electrical continuity between an integrated circuit chip (14) mounted on the top side, to other integrated circuit chips (16) mounted on the bottom side of the chipmount. Other conductive conduits (30, 32) and a bridging member (28) insulates intersecting conductive paths (48, 50). The micropackage is fabricated with standard silicon technology.

Abstract: The present invention provides syllable boundaries from a string of phonological linguistic unit indicia and word boundary data. The syllable boundary recognizer places a syllable boundary either at the next following word boundary or prior to the second vowel phonological linguistic unit indicia following the prior syllable boundary based upon the sequence of consonant phonological linguistic unit indicia prior to that second vowel. A permitted syllable initial consonant cluster includes an optional fricative consonant, an optional stop consonant and an optional sonorant consonant. The syllable boundary recognizer searches backward from the second vowel phonological linguistic unit indicia until the permitted sequence is violated, whereupon a syllable boundary is inserted. In the preferred embodiment, a refinement permits certain strong vowel phonological linguistic unit indicia to "capture" the following phonological linguistic unit indicia and shift the syllable boundary.

Abstract: A protective circuit arrangement is described for protecting semiconductor components connected to input and output terminals (10) against overvoltages in bipolar integrated circuits. The circuit arrangement contains at least one supply voltage terminal (12) and a ground terminal (14). Between the ground terminal (14) and at least the input and output terminals (10) which are connected to components sensitive to overvoltage a thyristor-tetrode (22) having a first control electrode (28) and a second control electrode (30) is inserted, the first control electrode (28) being connected to a line (18) which in the operative state of the integrated circuit lies at a voltage above the ground potential and the second control electrode (30) being connected to the ground terminal 14.

Abstract: An infrared imager, wherein a transparent gate is separated from a very narrow bandgap semiconductor (such as HgCdTe) by a thin dielectric. The gate is biased to create a depletion well in a semiconductor, and photo-generated carriers are collected in the well. The gate voltage is sensed to measure the accumulated charge. Preferably the accumulated charge is not sensed directly from the gate, but the gate output is repeatedly averaged with another capacitor, so that the output of the imager is sensed as an average over a number of read cycles, which provides a greatly improved signal-to-noise ratio. Preferably an array of the MIS detection devices is formed in a thin layer of HgCdTe, which is bonded to a silicon substrate containing a corresponding array of the averaging capacitors with addressing and output connections, and via holes through the HgCdTe are used to connect each detection device to its corresponding averaging capacitor.

Abstract: The projection display of the present invention employs a light source, a spatial light modulator such as a deformable mirror device having a plurality of individually electrically deformable mirror cells and Schlierin optics to project light from deformed mirror cells onto a viewing screen. An optical system forms light from the light source into a substantially collinear beam. A Schlierin optical device composed of alternating reflecting and transmitting portions is disposed at an angle to this beam. Light reflected or transmitted by the Schlierin optical device is focused by additional optics to a point near the deformable mirror device. Light reflected from undeformed mirror cells passes through the Schlierin optical device back to the light source. Deformed mirror cells reflect light at least in part to differing portions of the Schlierin optical device to follow a different path to a viewing screen.

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Abstract: A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.

Abstract: A plasma etch process for etching titanium nitride selectively with respect to titanium silicides. A reducing electrode, a low flow rate, and a non-copious fluorine source (such as CF.sub.4) are used to achieve a fluorine-deficient plasma. Preferably the substrate temperature is allowed to rise above 50 C during etching.

Abstract: Electron detector apparatus and method for detecting secondary electrons released from a body, of particular utility in testing integrated circuits in an operational state. The apparatus utilizes a magnetic lens having an axis of symmetry, for producing a magnetic field that progressively weakens along the axis, so that the secondary electrons travel through the magnetic lens in progressively elongated helical paths and approach an electron retarding means, for example a planar grid, at approach angles to the direction of the axis such that their approach speeds along the axis are substantially equal to their actual speeds. The secondary electrons are collected after passage through the retarding means.

Abstract: In a darlington transistor having an integrated resistor connected from base to emitter of the output transistor element, the effect of the diode between collector and emitter formed when the resistor consists of an extension to the base region is reduced by forming at least part of the resistor either as an extension to the emitter region or as a separate region of the same conductivity type and connected to it. The resistor formed by the emitter region material appears in series with the diode.

Abstract: A direct a.c. supply converter for converting an N (.gtoreq.2) phase input voltage system into an a.c. output voltage system of different frequency, amplitude, and/or phase using width-modulated contributions from the phases of the input voltage system to produce the output voltage system suffers from the disadvantage that the maximum output voltage amplitude can be limited to the minimum instantaneous voltage of the input voltage system because of the arbitrary timing relationship between the two voltage systems. This limitation is relieved by the addition of a component at the N.sup.th harmonic of the input system frequency to the width-modulation so that the effective minimum instantaneous voltage of the input system is increased. An increase in the maximum output voltage amplitude can also be obtained by adding to the width-modulation a component at the P.sup.th harmonic of the output system frequency; this can be used along or in conjunction with the component at the N.sup.

Abstract: A direct AC to AC supply converter in which the control of the bidirectional switches connecting each conductor of a polyphase input supply to each conductor of an output supply is effected by a data processor, the operation of the program of which is synchronized by interrupt with the input supply. The data processor calculates for each output phase 2 values representing pulse widths out of a repeating sequence of 3 (for three phase input and output supplies) and pulse generators produce 3 abutting width modulated pulses in a constant period much shorter than the periods of the supplies. The interrupt operates a software phase locked loop. The pulse generators include an interlock circuit ensuring that the width modulated pulses do not overlap and an overload detector responsive to the turn-on times of the switches. A default logic circuit responsive to hardward or software failure makes the width modulated pulses of equal duration.

Abstract: A high frequency amplifier comprising a pair of input transistors forming a differential amplifier stage, with an impedance connected between the common terminals of the input transistors to vary the amplification factor of the amplifier stage. The variable impedance is formed by a diode bridge the a.c. terminals of which are connected to the common terminals of the input transistors and the d.c. terminals of which are connected to a circuit arrangement including current mirrors to feed a d.c. current to the diode bridge to control its impedance and hence the amplification factor of the differential amplifier stage.

Abstract: A sampling switch circuit is provided for an analog to digital converter that provides for the scaling of two switches connected to the converter comparator. The comparator receives two input voltages which are switched to reference voltages. To correct any offset voltage resulting from a mismatch between the switch circuitry, this invention provides for one switch to be attached to a capacitor while the second switch is attached to the capacitive array that digitizes the analog input. These two switches are proportionally fabricated according to the size of their respective capacitive load in order to reduce any voltage difference resulting from the capacitive coupling internal to the switches. The switching circuitry also implements a sequence of switching to correct the offset error from capacitive coupling.

Abstract: A digital synchronizer includes a latch connected to a level sensitive circuit. The latch is constructed to provide a rapid transition between logic "0" and logic "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from logic "0" to logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for 3/4 of a machine cycle to allow any transients conditions within the latch to dampen out.

Abstract: A direct AC converter for converting a polyphase AC input supply into an output DC or single or polyphase AC supply of amplitude, phase, frequency or power factor which is different from the input supply using a matrix of bidirectional switches having contiguous width modulated conduction periods in cycles which synthesize the output supply voltage or voltages from samples of the input supply voltages taken cyclically at a much higher frequency than the supply frequency or frequencies. The switches are operated so that the or each output supply conductor is connected to only one of the input supply conductors at a time. The width modulation may be effected in response to phases of a sinusoidal oscillation to produce a frequency change. The output may have a "negative" frequency so that a phase displacement between current and voltage due to a reactive load appears in the opposite sense in the input supply.

Abstract: MESFET devices are fabricated on a semiconductor substrate using a LOCOS (localized oxidation of silicon) process twice during the fabrication. The first LOCOS process provides device separation with a self-aligned thick-field oxide (SATO). The second LOCOS provides separation of gate and source/drain regions for each device, and self-aligns the gate contact with the channel implant. Devices fabricated by this method exhibit reduced series resistance, and improved metal step coverage.

Abstract: Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that a charge is given to the nonvolatile multidielectric stack between the MIS gate and the JFET source of the cell. For a charge of one polarity, an inversion layer of electrons (for a P-type substrate) is formed on the surface of the JFET source, increasing the capacitance between the MIS gate electrode and the JFET gate electrode. For the opposite polarity, an accumulation layer forms at the JFET source surface, decreasing the interelectrode capacitance. The cell is read by presetting one address line, floating that line, then putting a pulse on the other line while reading the voltage output on the floating line.

Abstract: An analog to digital converter is provided which includes a binary weighted capacitor array connected with a series of resistors structured as an array. The converter provides for charge correction to compensate for any capacitance deviation in the capacitor array. The converter includes a charge redistribution sequence under the control of a microcomputer to determine the digital value of the analog input using the resistor array to determine the least significant bit positions of the analog input. This same resistor array is also used to correct for capacitor value deviations in the binary weighted capacitor array.