Abstract: A synchronous circuit system comprises a switch circuit for receiving an asynchronous imput signal only within a specified period in response to a synchronizing signal, a latch circuit connected to the switch circuit, a signal transmission circuit connected to the output of the latch circuit and adapted for holding the logic state thereof as before until a necessary input level of the asynchronous input signal is reached, and a feedback circuit connected between the output of the latch circuit and the output of the switch circuit.

Abstract: Method of encoding speech signals which is based upon determining the roots of the linear prediction polynomial describing the spectrum of an analog speech signal, wherein the roots are candidates in determining the formants of the speech signal. The method involves the analysis of respective frames of sampled digital speech data using a linear predictive technique to determine a set of reflection coefficients or K-parameters which are then converted into the equivalent predictor coefficients or A-parameters describing a prediction polynomial having a plurality of roots corresponding to the poles of an all-pole filter characterizing the vocal tract. A modified Bairstow technique is then empolyed for factoring out quadratic factors which are then sorted in an ordered arrangement in terms of ascending bandwidths.

Abstract: An integrated circuit is described which includes a plurality of output transistors (T1, T2, . . . Tn) for emitting binary signals to associated output terminals (A1, A2, . . . An). The integrated circuit further includes at least one ground terminal (M; M1, M2 . . . Mn). Between the base of each transistor (T1, T2, . . . Tn) and the at least one ground terminal (M; M1, M2, . . . Mn) a current source (R1, D1) controlled by the base voltage is inserted.

Abstract: A speech encoding process, wherein a first sequence of input data representative of a written version of a message to be coded is encoded to provide a first encoded speech sequence corresponding to the written version of the message to be coded, and a second sequence of input data derived from speech defining a spoken version of the same message is analyzed by a linear predictive codeing analyzer and encoding circuit to provide a second encoded speech sequence corresponding to the spoken version of the message to be coded. The codes of the corresponding written message and the codes of the spoken message are then combined in a control circuit encompassing an adaptation algorithm, and a composite encoded speech sequence is generated corresponding to the message from the combination of the first encoded speech sequence of the written version of the message and encoded intonation parameters of speech included in a portion of the second encoded speech sequence corresponding to the spoken version of the message.

Abstract: The mode of operation of an intergrated circuit capable of several modes of operation is determined by at least one signal applied to one or more mode selection terminal pins. The signal applied is a selected one of at least two signals derived from a clock signal used by the integrated circuit in its operation. The clock signal is generated by an oscillator which may be included in the integrated circuit or external to it; in either case, the clock signal appears at another terminal pin of the integrated circuit.

Abstract: A semiconductor device is primarily composed of a semiconductor substrate of a first conductivity type and a semidonductor layer of a second conductivity type formed in a principal plane of the semiconductor substrate. The device has both a bipolar transistor with the semiconductor layer itself being the collector region. The base region is of the first conductivity type and the emitter region is of the second conductivity type. Both regions are formed in the same layer as a JFET struture which includes the above collector region as channel a and the above base region as a gate. A semiconductor region of the first conductivity type is formed in the above semiconductor layer, the semiconductor layer itself, and the above base and emitter regions constitute a thyristor structure.

Abstract: A method of passivation of Hg.sub.1-x Cd.sub.x Te and similar semiconductors by chemical reaction to either sulfide or selenide or a combination of both with an oxidizer such as polysulfide or polyselenide ions in solution.

Abstract: A method of diffusion of dopants (e.g. zinc) into III-V substrates (e.g. GaAs) using metal silicide and dopants (e.g. W.sub.x Si.sub.y :Zn) is disclosed. A cap layer (e.g. SiO.sub.2 or Si.sub.3 N.sub.4) is also used. The zinc tungsten silicide is formed by cosputtering zinc and tungsten silicide (W.sub.5 Si.sub.3). Applications include adjustment of threshold voltages in JFETs by rapid thermal pulsing of zinc into device channel regions and use of the zinc tungsten silicide as a base contact plus extrinsic base dopant source together with a nitride sidewall self-alignment.

Abstract: A complete integrated circuit processing module, wherein multiple processing stations, each with its own vacuum isolation, are located inside a single module which is held at hard vacuum. A wafer transport arm mechanism permits interchange of wafers among the processing stations and a load lock. The load lock is equipped to remove and replace wafers from a vacuum-sealed wafer carrier. The wafers remain face-down and under hard vacuum during all the wafers handling steps.

Abstract: A multiport random access memory cell includes a current mode latch (68) for storing two logic states and interface circuits for interfacing the input of the latch (68) with multiple input ports and the output of the latch (68) with multiple output ports. The interface circuitry comprises current switches (70-76) for switching current to a current source in the presence of a write select and a row select signal to override the holding current in the current mode latch. The output interface circuitry includes current sensors (78-84) for sensing the logic state in the latch and outputting it to the select output ports in the presence of a row select signal. The current switches and the current sensors utilize current mode logic and with a common current source. The current source is disable in the absence of any row select signal such that power is not drawn by the memory cell in the unselected state.

Abstract: A circuit board system resiliently mounts a plurality of daughter boards with high circuit interconnection density on a mother board using pairs of mating connectors having welded contact members accommodated in novel arrangements in the respective connectors to permit high density of electrical interconnection with convenience and reliability. Contact parts of substantial size are welded into contacts in one connector to detachably interconnect with contact parts of similar size in mating connector to improve interconnection releability. Novel contact arrangements permit accommodation of those parts of substantial size in the mating connectors. Sheet metal spring or post parts welded into the contacts in both connectors permit the contacts to be conveniently loaded into connector bodies and permit large numbers of contact springs or posts to be soldered to terminal pads or circuit paths on mother or daughter boards with high density.

Abstract: An article gripper assembly comprising a support member, a movable base member movable back and forth in a predetermined direction with respect to the support member, a pair of finger members movable toward and away from each other with respect to the base member in opposite directions parallel with the predetermined direction, a rotatable member rotatable about an axis fixed with respect to the base member and substantially perpendicular to the predetermined direction, link members coupling the rotatable member operatively to the finger members for converting rotation of the rotatable member in one direction about the axis of rotation of the rotatable member into movement of the finger members toward each other with respect to the base member and rotation of the rotatable member in the opposite direction about the axis of rotation of the rotatable member into movement of the finger members away from each other with respect to the base member, a pair of centering members fixedly positioned with respect to the

Abstract: A method of passivation of HG.sub.1-x Cd.sub.x Te by anodic selenidization is disclosed; in preferred embodiments the selenidization is by anodic growing of the selenides in an electrolyte solution of sodium selenide in water and ethylene glycol or in a solution of sodium selenide plus sodium hydroxide in water and ethylene glycol. Also, infrared detectors incorporating such selenide passivated Hg.sub.1-x Cd.sub.x Te are disclosed.

Abstract: A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V.sub.cc power supply and ground (32) nodes by using a "graded turn-on." Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.

Abstract: A multiple oscillator switching circuit for a digital processing system that includes a central processing unit having a first internal timing cycle and connected to a plurality of peripheral devices, each peripheral device having an independent internal timing cycle. The central processing unit is further connected to an oscillator switching circuit. The oscillator switching circuit includes several oscillators. Each oscillator has an output consisting of an independent internal frequency. A selected number of these oscillators have independent internal frequencies that correspond to the internal timing of the peripheral devices. These oscillator switching circuits are further connected to the central processing unit and to the output of each of the oscillators for providing a single oscillator output to the central processing unit in response to an output from the central processing unit.

Abstract: A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

Abstract: Speaker-independent word recognition is performed, based on a small acoustically distinct vocabulary, with minimal hardware requirements. After a simple preconditioning filter, the zero crossing intervals of the input speech are measured and sorted by duration, to provide a rough measure of the frequency distribution within each input frame. The distribution of zero crossing intervals is transformed into a binary feature vector, which is compared with each reference template using a modified Hamming distance measure. A dynamic time warping algorithm is used to permit recognition of various speaker rates, and to economize on the reference template storage requirements. A mask vector with each reference vector on a template is used to ignore insignificant (or speaker-dependent) features of the words detected.

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO2 hard mask. The SiO2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiOx (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: An injection mold is described for producing the housings of integrated circuits. The injection mold icludes a first mold half (30) in which are disposed a number of mold recesses (46) corresponding to the number of housings to be made simultaneously, having a depth corresponding to a portion of the height of the housings, and supply passages (48, 50, 52, 54, 56, 58) leading to the mold recesses (46). In a second mold half (32) which is adapted to be brought in the closure direction into engagement with the first mold half (30) a number of mold recesses (76) equal to the number in the first mold half (30) are disposed in corresponding arrangement, the depth thereof being equal to the remaining portion of the height of the housings to be made. The mold recesses (46) in one of the mold halves (32) are disposed groupwise in mold portions (64) which are held in the one mold half (32) displaceably in the closure and opening direction.

Abstract: The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.