Abstract: A fast light interconnected processor device for image processing includes an image sensor for producing a line scan signal, a one-dimensional line display for producing a light having an intensity representative of the scan signal and an array of light detectors for producing a two-dimensional convolution of the image with a blurring function performed simultaneously with the scanning of the image scene. The image sensor is, for example, a thermal imager (forward looking infrared system) which outputs electrical signals representative of thermal energy emanating from a scene. The one-dimensional line display is, for example, a one-dimensional array of light emitting diodes which converts the electrical signals of the thermal image to a light image.

Abstract: Solar cells are formed of semi-conductor spheres of P-type interior having an N-type skin are pressed between a pair of aluminum foil members forming the electrical contacts to the P-type and N-type regions. The aluminum foils, which comprise 1.0% silicon by weight, are flexible and electrically insulated from one another. The spheres are patterned in a foil matrix forming a cell. Multiple cells can be interconnected to form a module of solar cell elements for converting sun light into electricity.

Abstract: A humidity sensor composed of interdigitated electrodes and a material therebetween which is composed of Nafion wherein H+ cites have undergone ion exchange with at least one of NH4+ and Li+, Na+, Ag+ and Mg+.

Abstract: A printed circuit board connector is shown having an elongated body of electrically insulating material in which several rows of apertures extend from a flat surface on one side, each row extending to one of a series of platforms on an opposite side spaced at progressively greater distances from the flat surface in order to accommodate contact pins having right angle bends with the same spacing beyond the right angle bend as on the flat surface. The contact pins received in the apertures communicating with the flat surface may be of the male pin or female receptacle type.

Abstract: A procedure for planarizing a group II-VI composition which includes a resist and etch-back procedure wherein a thick resist coating relative to the degree of non-planarity is spun over a non-planar group II-VI layer to provide a planar resist surface. The resist is then etched back to the group II-VI layer with etching of both the resist and the group II-VI layer then continuing simultaneously and at substantially the same etch rate until all of the resist has been removed. The etching takes place in a chamber having a parallel plate RF plasma etcher using a dry etchant which uses the RF plasma. The etchant is a hydrogen and oxygen combination at low pressure which is activated by the RF excitation. An inert gas, preferably argon, and methane can optionally be added to the gas flow. The flow rate at each inlet is continuously adjustable. The flow of gas into the chamber continues while the chamber is also being pumped simultaneously to maintain the desired pressure within the chamber.

Abstract: Field effect transistors in which the channel region is made of thin highly doped polysilicon which is preferably also hydrogen passivated.

Abstract: Layered arrays of nearest-neighbor connected computation cells plus an error computation layer provide a learning network.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: A method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30 . Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Abstract: A sub-miniature circuit breaker particularly suited for use with aircraft simulators is shown which has the same look and feel of circuit breakers used in aircraft. The circuit breaker has a push-pull/actuator and ball latch mechanism and a solenoid operated trip mechanism.

Abstract: There is disclosed a manufacturing method and apparatus which allows for the efficient assembly of the exposure module of a xerographic reproduction system. The system uses an array of deformable mirrors fabricated in one embodiment, on a monolithic silicon substrate as a light modulation element. The substrate package is positioned with respect to a set of molded support brackets such that a multi-axis adjustment of this single element allows for the alignment of the entire optical set. A system of cameras is used, in conjunction with a computer, to control the substrate positioning and to determine optimum efficiency of the system. The computer adjusts the package around the various rotational axis in sequential fashion.

Abstract: A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.

Abstract: DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.

Abstract: A pressure responsive switch having upper and lower contact assemblies with a snap acting member and an electrically conductive member sandwiched therebetween. The assemblies each include an insulating body with a hollow center and an electrically conductive member having a contact in the center portion and extending externally of the body. The snap acting member is in constant engagement with the sandwiched conductive member and normally in engagement with the electrically conductive member of the upper assembly. When a pressure is applied which is sufficient to cause the snap acting member to snap into its second stable state, the connection thereof with the electrically conductive member in the upper contact assembly is broken and connection is made with the electrically conductive member in the lower assembly. The switch is normally closed by removing the portion of the electrically conductive member in the lower assembly which extends externally thereof.

Abstract: First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance.

Abstract: An electronic circuit device wherein lines are provided to connect elements, and wherein a plurality of island shaped non-line parts, which do not have the function of the lines, are formed along the length of the lines.

Abstract: A connector for mounting an i.c. unit on a circuit board is made by providing an electrically insulating, thermoplastic body with a plurality of apertures arranged in a pattern and with contact members disposed in the apertures so that terminal portions of the members extend from the apertures at one side of the body. A heated tool having hollow cylindrical portions spaced in the same pattern at one side of the tool is advanced to accommodate the extending terminal portions of the contact members in the hollow portions of the tool and to engage ends of the hollow cylindrical tool portions with individual parts of the body surrounding the respective apertures.

Abstract: Hot-electron-induced degradation of a semiconductor device (10) is reduced by converting the silicon surface (18) to a fluorinated-silicon compound interface region (23). The fluorinated-silicon compound interface region (23) is formed by etching the device (10) in a fumer (30) using anhydrous hydrofluoric acid. After a sacrificial oxide is grown over the silicon surface (18), the device (10) is placed in a container (32). A mixture of nitrogen, moistened nitrogen and nitrogen/anhydrous hydrofluoric acid is injected into the container (32) to conduct the etch. The anhydrous hydrofluoric acid converts the silicon to a fluorinated-silicon compound, such as H.sub.2 SiF.sub.6, and water. The fluorinated-silicon compound interface region (23) has stronger molecular bonds than the typical hydrogen-silicon formed at the oxide/silicon interface and is, therefore, less likely to be broken apart by hot-electrons.

Abstract: A process for silylation of positive or negative photosensitive resist layer on a semiconductor wafer after the resist layer has been exposed to radiant energy through a mask which includes introducing a silylating agent to the wafer at high pressure over 760 torr and, usually, at temperatures less than 180.degree. C. Increased pressure increases the rate of silylation, allows practical use of lower process temperatures, and, therefore, allows better process control. Also an apparatus is disclosed for applying the high pressure silylation process to a wafer.

Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the I-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.