Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may also be integrated on the substrate.

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

Abstract: A supplementary heating system particularly suitable for an automotive vehicle comprises a step down transformer coupled to the stator windings of the vehicle's alternator and a positive temperature coefficient (PTC) of resistivity heater electrically connected intermediate the stator windings and the transformer in parallel with the transformer. Due to the presence of the transformer the voltage regulator causes the alternator to operate at a higher than customary voltage to provide the conventional 14.4 volts for the vehicle's normal electrical loads with the high voltage used to energize the heater. The heater can be in the form of a so-called "honeycomb" having a plurality of parallely extending passages or cells disposed in the air stream going from the main heater into the passenger compartment and can be either a multiphase, single phase or direct current type.

Abstract: Method of encoding speech at medium to high bit rates while maintaining very high speech quality, as specifically directed to the coding of the linear predictive (LPC) residual signal using either its Fourier Transform magnitude or phase. In particular, the LPC residual of the speech signal is coded using minimum phase spectral reconstruction techniques by transforming the LPC residual signal in a manner approximately a minimum phase signal, and then applying spectral reconstruction techniques for representing the LPC residual signal by either its Fourier Transform magnitude or phase. The non-iterative spectral reconstruction technique is based upon cepstral coefficients through which the magnitude and phase of a minimum phase signal are related. The LPC residual as reconstructed and regenerated is used as an excitation signal to a LPC synthesis filter in the generation of analog speech signals via speech synthesis from which audible speech may be produced.

Abstract: A two transistor gain-type DRAM cell (8) is formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).

Abstract: The disclosure relates to a circuit and method of reducing inductive voltage spikes caused by an abrupt change in current by an output transistor, by providing an input node for receiving an input voltage signal, providing an output node, providing a first transistor coupled to the output node, receiving a predetermined voltage at the input node, controlling voltage control circuitry coupled between the input node and the first transistor and responsive to the predetermined voltage at the input node to control the voltage driving the first transistor with respect to time to provide a constant rate of change of current with respect to time in the first transistor and providing a second transistor coupled to the output node in parallel with the first transistor which turns on prior to the first transistor.

Abstract: Hysteresis effects in low frequency field effect transistor circuits are minimized by using biasing or clamping circuits including field effect transistors.

Abstract: A technique for analyzing defective semiconductor chips is disclosed. The silicon substrate of the chip is etched away, leaving the memory cells exposed for viewing. The method includes the steps of: removing oxide from the backside of a semiconductor device; and, placing the semiconductor device into a solution of choline and water. The solution etches away the substrate. The memory cells may be photographed and viewed by TEM and SEM techniques.

Abstract: A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of a second conductivity-type. An interface 36 having interfacial traps is formed between current path 32 and substrate 26. A backgate 24 is formed adjacent substrate 26. A first switch 14 selectively couples backgate 24 to a first voltage while a second switch 16 selectively couples backgate 24 to a second voltage.

Abstract: A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS gate conductors and a bipolar emitter structure is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes, and another high impurity concentration area which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips. Alignment of electrode metallization patterns is thus less critical.

Abstract: An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuits. A shallow recess (56) is then formed simultaneous with a stepped sidewall structure of the deep trench. The recess (56) and the trench (46) are covered by an insulating oxide (60). and thereafter filled with an undoped polysilicon (62) to form the different isolating structures for the different types of circuits.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter strucure (60). A collector region (90) and an extrinsic base region (100) are formed in the semicondcutor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) are disposed to create inversion regions, of a second conductivity type opposite said first conductivity type, in the underlying source inversion region (40) and drain inversion region (42) of semiconductor layer (12) upon application of voltage. The transistor has a gate (54) insulatively overlying the channel region (44) to control the conductivity thereof.

Abstract: A calibration method for a phased array antenna uses automated signal processing techniques to compute calibration coefficients, and can be performed while the antenna is on-line. The calibration method is based on a generalized model in which the array is characterized by a phase-state control function. The calibration coefficients for a phase shift element are computed using phase response measurements derived from an estimation of the residual aperture response attributable to the other elements. For each element of the array, a first set of I Q aperture response measurements is used to estimate (FIG. 1a, 10) the R.sub.I and R.sub.Q residual components of the total I Q aperture response attributable to the other elements. Using these residual components, a second set Y of I Q aperture response measurements is converted (FIG. 1b, 20) to measurements of the phase response attributable to the selected element. From these phase response measurements, the calibration coefficients .phi..sub.

Abstract: The disclosure relates to the article and a method of forming a field oxide which extends over an isolation trench and the adjacent substrate wherein a portion of the trench insulating sidewall at the top region thereof is removed and replaced by polysilicon. The exposed silicon on the substrate and adjacent polysilicon are than oxidized to form the field oxide which is continuous, disposed above and contacts the remaining sidewall insulator in the trench.

Abstract: A pressure sensing element having a housing including a flexible membrane receiving portion, a flexible disc member of predetermined shape secured within the housing, and a flexible membrane disposed within the housing, the flexible membrane being substantially more flexible than the disc member, the membrane having an outer portion hermetically secured to the membrane receiving portion, a central portion impinging against the disc member and conforming to the shape thereof and an intermediate unsupported portion joining the interior portion of the outer portion and the exterior portion of the central portion.

Abstract: An electrostatically deflectable beam spatial light modulator with the beams (30), address electrodes (42, 46), and landing electrodes (40, 41) to provide soft-landing of the beams on the landing electrodes (40, 41) which gives uniform large-angle deflection plus high reliability.

Abstract: A shell having symmetrical top and bottom parts form a chamber containing a substrate carrying package semiconductor devices and a connector. A cover fits in a hollow of the top part normally for its top surface to rest flush with the top surface of the top part. The packaged semiconductor devices on the substrate extend through apertures in the top part with the top surfaces of the packaged semiconductor devices resting substantially flush with the top surface of the top part. The cover flexes over the packaged semiconductor devices at those locations. Gripping means occur in the ends of the shell opposite the connector to aid removal of the memory card from a desired port and an interior wall and side pockets provide stress relief for removal and insertion of the connector in the desired port.