Abstract: An active pull down circuit for a logic circuit, having a true and a complement output, a pull down transistor coupled to one of the true and complement outputs, a bias element for biasing the pull down transistor on, and a charge coupling element coupled between the other of the true and complement outputs and a base of the pull down transistor for coupling charge from the other output to the pull down transistor to turn on the latter harder when the other output goes low.

Abstract: This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g.

Abstract: A transponder includes a receiving and evaluating section (22) andd a transmitting section (28). It further includes an energy storage means (18) which is chargeable by an HF interrogation pulse furnished by an interrogation device and supplies the supply voltage for the receiving and evaluating section (22) and for the transmitting section (28). An identification generator (30) in the transponder furnishes identification data fixedly associated therewith and a measurement data generator (32) receives from a sensor (34) measurement signals and converts said measurement signals to measurement data. The receiving and evaluating section (22) clears the transmitting section (28) for transmitting the identification data only when the supply voltage exceeds a first predetermined threshold value.

Abstract: A test set socket adaptor (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adaptor (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate for variations in solder bumps (26) on the bare chip (22). The deflection of the cantilever beams (32) allows a positive contact between the solder bumps (26) and the cantilever beams for an AC and a burn-in test.

Abstract: The invention is structured to add each output signal of a plurality of signal converters connected in parallel, after a common signal is inputted to and quantized in the above plurality of signal converters, having a noise generators which input noise generated utilizing random variables unrelated to each other to respective quantizers within the above plurality of signal converters, so that quantization noise, Q, or the like can be effectively averaged, and a highly reliable signal conversion device, which can ensure an enough dynamic range across a wide frequency region, can be provided.Also, the invention is structured to add each output signal of a plurality of signal converters connected in parallel, after a common input signal is inputted to and quantized in the above plurality of signal converters, so that a highly reliable signal conversion device similar to the above can be provided.

Abstract: A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked--a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

Abstract: A data processing device includes an instruction decoder and an arithmetic logic unit having first and second inputs and an output. An accumulator is connected between the output and first input of the arithmetic logic unit. A further register is connected between the accumulator and the second input of the arithmetic logic unit. The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as well as an additional circuit. The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command. Other devices, systems and methods are also disclosed.

Abstract: There is disclosed an exposure unit and method of operation having advantage of deformable mirror device (DMD) technology. The exposure unit is used to provide front end image processing for a xerographic process printing system. The unit, in one embodiment, is constructed as a unitary member having a lamp socket, a support for holding a flat DMD substrate, a set of light focusing lenses, an image focusing lens, a light baffle and an extra light trap chamber. The unit is separated from the xerographic drum by a solid base which contains a slot positioned so that the image from the image lens passes therethrough for supplying the image to the drum. The light bundle is directed to the xerographic drum location along an optical path formed by a system of fold mirrors in the lower body of the unitary member.

Abstract: A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.

Abstract: This digital-analog conversion system comprises a digital modulator (1) having several quantification levels formed by a second order Delta-Sigma modulator and a digital-analog converter and switched capacitors filter set (3) whose law of progression between the different analog levels is independent of the absolute and relative values of the constituent components of the said assembly.

Abstract: An apparatus for treating an object with a liquid in which the object is immersed into the liquid in a tank which has overflow control members provided above faces of the tank with a predetermined space in an overflow area for said liquid, said space being structured to lead the overflow of said liquid by capillary action.

Abstract: A method is provided for synchronizing the time scale of a test device driver (12) with an e-beam tester. Test device driver (12) generates a test pattern which is applied to the functional inputs (18) of a device under test (16). A trigger and a synchronizing signal are generated with an identical time relationship to the test pattern. The trigger is applied to the trigger input of e-beam tester electronics and e-beam generator (38). The synchronizing signal is caused to appear on device under test (16). Using e-beam tester electronics and e-beam generator (38), waveforms are created of the synchronizing signal appearing on device under test (16) and test response signals also appearing thereon in response to application of the test pattern to functional inputs (18). The time relationship between the synchronizing signal and the test response signals can then be established through the waveforms.

Abstract: The described embodiments of the present invention provide a structure and method for easily incorporating a high voltage lateral bipolar transistor in an integrated circuit. A buried base contact is formed and the base itself is formed of a well region in the integrated circuit. An oppositely doped well region is formed surrounding the collector region in the lateral PNP transistor. This collector well is formed of the opposite conductivity type of the base well. Contact to the collector and a heavily doped emitter are then formed in the collector well and base well, respectively. The more lightly doped collector well provides a thick depletion region between the collector and base and thus provides higher voltage operation. The positioning of the base/collector junction to the collector well at base well junction also reduces the spacing between the collector and the emitter.

Abstract: A method of making single crystal semiconductor grade silicon spheres for solar cells and the like from metallurgical grade silicon. The process comprises sizing metallurgical grade silicon particles to a desired range and oxidizing the outer surfaces of the particles to form a silicon dioxide skin thereon. The particles are then heated to melt the silicon within the skin to cause impurities to travel into the skin. This is made possible because single crystals are formed. The skin and impurities therein are then etched off and the remaining particles are again treated to form a skin with subsequent melt of the interior silicon and removal of the skin, the cycle being repeated until the desired degree of silicon purity is obtained. An intermediate shotting step can yield spheres of substantially uniform diameter for use as the feed for the repeat cycle.

Abstract: A signal transmission circuit (10) for transmitting a signal (V.sub.IN) between dies on a wafer. A transmission node (72) is precharged to a first voltage (70) that is representative of a first of a plurality of bit values in response to the actuation of a gate (48) of a P-channel transistor (50) by a first state control signal (.phi..sub.1). At a later time, a second state of the control signal (.phi..sub.1) actuates a pass gate transistor (38) to couple the end of a first transmission signal line segment (32) to a node (40). A preselected state of the node (40) will cause the signal node (72) to be grounded to a logic zero (74). The signal node (72) is selectively coupled to a latch (92) by a one-shot pass gate (76). The output (102) of the latch (92) is connected to the beginning end of a second transmission line segment (104). The transmission of the signal thus relies on the state of the signal node (72) rather than on the presence or absence of a connection directly to a voltage supply such as V.sub.dd.

Abstract: An apparatus and method for translating voltages between logic levels is provided having an input section (11), a level shifter section (89) and an output section (137). Input section (11) provides two control voltages to the level shifter section (89) in response to an input signal provided at input terminal (12). Level shifter section (89) comprises two inverters coupled to the control voltages. One inverter comprises p channel field-effect transistor (90) and n channel field-effect transistor (98). Another inverter comprises p channel field-effect transistor (106) and n channel field-effect transistor (114). For each inverter, the channel of the p channel field-effect transistor is over twice as wide as the channel of the n channel field-effect transistors. Each transistor (90, 98, 106 and 114) conducts current in response to a control voltage being anywhere within the voltage range, such that outputs of the inverters transition quickly in reponse to a transition of the control voltages.

Abstract: A lead from 10 carries an integrated circuit on a die support pad 14. The lead frame has a dam bar including a transverse portion that extends between adjacent leads (20) for limiting mold flash. The dam bar transverse portion 26 is entirely severed from the adjacent leads for final removal by a metal punch 33 along with the supporting web 16.

Abstract: An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.

Abstract: A supplementary heating system particularly suitable for an automotive vehicle comprises a step down transformer coupled to the stator windings of the vehicle's alternator and a positive temperature coefficient (PTC) of resistivity heater electrically connected intermediate the stator windings and the transformer in parallel with the transformer. Due to the presence of the transformer the voltage regulator causes the alternator to operate at a higher than customary voltage to provide the conventional 14.4 volts for the vehicle's normal electrical loads with the high voltage used to energize the heater. The heater can be in the form of a so-called "honeycomb" having a plurality of parallely extending passages or cells disposed in the air stream going from the main heater into the passenger compartment and can be either a multiphase, single phase or direct current type.

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.