Abstract: A monochrome image becomes expanded into a color image for storage in a bit mapped color display memory. The color expand operation substitutes color data of one of two designated colors for the "1" or "0" monochrome data of a stored monochrome image. The first color code is substituted for all pixels of the monochrome image represented by a "1" and the second color code is substituted for all pixels of the monochrome image represented by a "0". This color expanded image is then stored in the color display memory which controls the color picture shown to the user. This technique permits storage of commonly used images such as alphanumeric characters of various fonts or icons in a compressed form with one bit per pixel. These images are formed in color using the color expand operation at the time of drawing into the color display memory. Otherwise these images would need to be stored in multiple bit per pixel color form for all desired colors requiring considerable memory for redundant data.

Abstract: A T-shaped trench intersection shaped to make uniform the wall-to-wall spacing at the trench intersection and prevent the formation of voids when the trench is filled with a conformal insulating material.

Abstract: A method for storing and accessing data in the operation of a program driven computer system for carrying out an industrial process, which system includes a non-volatile, long access time memory medium and a volatile, short access time memory medium, which method includes: configuring the non-volatile and volatile memory media into a unitary, relational database composed of a plurality of tables each composed of an ordered set of data elements; storing in the non-volatile memory medium a set of data elements which forms at least a first table of the database and which is required by the process infrequently and/or need not be accessed rapidly; storing in the volatile memory medium a set of data elements which forms at least a second table of the database which must be rapidly accessed; executing a plurality of programs in cooperation with data elements forming the database in order to control the process; and establishing communication between the programs and the database via an interface which causes the pr

Abstract: A capacitive acceleration sensor using a common PWB as one of the plates of the capacitive transducer and the wiring connections thereto. An acceleration input moves a capacitor plate to produce a measurable change in capacitance. An electronic signal conditioner accurately converts the capacitance output to a voltage signal to provide an acceleration sensor featuring accurate DC performance. The transducer and electronics are disposed on a PWB making up a complete sensor package. In a first embodiment, the capacitor comprises a fixed electrode on the PWB and a movable acceleration responsive electrode secured to a support by a conductive resilient member, the support coupled to an electrically conductive region on the PWB spaced from the fixed electrode by a guard ring to minimize stray charge between the capacitor electrodes.

Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system.

Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a sub-picture and a full size picture may be displayed at one time.

Abstract: A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total thickness less than 250 .ANG.. A doped third semiconductor layer formed over the second layer. The net has a dopant concentration in the second layer is greater than the net dopant concentration in the third layer. A gate layer is positioned over the third layer. In a preferred embodiment the second layer is a pulse-doped pseudeomorphic material. There is also provided a method for making the heterostructure field effect transistor. A doped pseudomorphic semiconductor layer of a first conductivity type is formed between first and second other semiconductor layers, the second layer including a net dopant concentration of the first conductivity type. A Schottky gate electrode is formed in contact with the second layer.

Abstract: A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor has its gate connected to the input node and switches hard on when the input node goes to a high level, pulling the reference node to a low level. A second current mirror is provided which injects current into the reference node for a predetermined period of time after the voltage level at the input of the buffer goes to a low level to pull the reference node to a high level. Both the first and second current mirror are switched on only during transition states of the input buffer, to minimize power dissipation when the input buffer is in its quiescent state.

Abstract: An advanced video processor generates displays for displaying of either graphics or text information via a display monitor or a TV set operating as a monitor. A color palette is included in the advanced video processor for programming of the color of the display. The color palette provides 512 color selections, any sixteen of which may be displayed at once.

Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

Abstract: An internal combustion engine has a channel member such as a plenum chamber or cylinder head or the like with an inlet receiving air and fuel to form an air-fuel mixture and with a pair of outlets furnishing the air-fuel mixture to respective cylinders or groups of cylinders or to respective cylinder intake valve openings of two-intake engine cylinders or the like. A heating device mounted on the channel member has a heat-exchange surface which intercepts the air and fuel from the inlet to heat and fully vaporize the fuel to form the air-fuel mixture and also to divide the fuel mixture between the two outlets for furnishing the fuel mixture to the individual cylinders, groups of cylinders or intake valve openings.

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Abstract: A method for applying a dielectric material to a solar array having an edge, a light gathering side and a backside, which includes the steps of sealing the array along the array edge, providing a gas pressure differential between the light gathering side and the backside which pressure is greater on the light gathering side than on the backside and applying the dielectric material to the backside of the array wherein the gas pressure differential is sufficient to substantially prevent the dielectric material from leaking from the backside to the light gathering side.

Abstract: A device for tracking an object (12) in three dimensional space is provided which comprises a fiber optic sensor array (14). Fiber optic sensor array (14) comprises a row plane (16) and a column plane (18) each comprising a plurality of parallel optical fibers bonded together. A row detector (20) is coupled to the ends of the fibers comprising row plane (16). A column detector (22) is coupled to the ends of the fibers comprising column plane (18). Row and column detectors (20) and (22) are coupled to a decoder circuit (24). First and second beam generators (26) and (28) are affixed to the object (12) and are each operable to transmit beams (30) and (32) which terminate on the fiber optic sensor array (14). By determining the points of incidence of beams (30) and (32), the decoder circuit (24) may determine the position of the object (12) in three dimensional space.

Abstract: A plasma flow is uniformly distributed over the surface of a water (76) by an L-shaped tube (64) and a distribution ring (62). A dispersal gas, which may either comprise an inert gas or a gas that cooperates with the reactive species of the plasma, is sprayed from the tube (64) and the ring (62) into the flow of the plasma. The ring (62) comprises a hollow tube encircling the outlet of a plasma reactor. A gas is circulated through the ring (62) within the hollow interior (66) and is emitted therefrom by nozzles (70). The tube (64) comprises a quartz or anodized aluminum L-shaped tube which is positioned directly in the flow of the plasma. The gas is emitted from the tube (64) in a direction directly opposite and into the flow of the plasma.

Abstract: Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Abstract: A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

Abstract: An integrated circuit device is disclosed. In one embodiment, the device has a semiconductor chip having an electrical circuit that is connected to a bonding pad. A metal layer overlies the bonding pad, and a metal bump is connected to the metal layer. The metal bump receives power for the electrical circuit. The method of manufacture allows a designer to form a power supply bus in the metal layer. The metal layer may lie over an active circuit of the semiconductor chip.

Abstract: Preferred embodiments mask select regions of a circuit surface (141) prior to abrading the surface with diamond particles to form nucleation sites (200). The mask (150) is then removed prior to forming a diamond layer (160). Diamond layer (160) grows on the surface except in those regions wherein the mask (150) prevented the formation of nucleation sites (200).