Abstract: A system and method which assumes that the process being evaluated is written in a highly concurrent language or at least is capable of high degree of concurrent operations. The parameters employed in the simulated concurrent performance have a direct affect on performance time.

Abstract: An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.

Abstract: A task control mechanism for maintaining a queue of ready or available processes linked together according to an assigned priority for a plurality of central processors where the processors may be assigned to the highest priority task when that processor is not busy executing some higher priority task. The task control mechanism also includes a mechanism for computing task priorities as new tasks are inserted into the queue or removed. The mechanism also maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

Abstract: An event allocation mechanism in a processing system which mechanism maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

Abstract: A referencing unit which creates addresses for main memory. Specifically, this reference unit is pipelined in the manner in which it receives the operators to be executed. Concurrency is achieved by allowing any number of read-type operations to be started before operators that are waiting for a store operation to finish even though these latter operators may appear earlier in the code stream. There are two inputs into the reference unit. Each is provided with a queue, one for receiving operators and address couples and another for receiving the output from the top-of-the-stack mechanism residing in the processor. The former is called an address coupled queue and the latter is called a top-of-stack queue. Since the address couple queue operators require no stack inputs, they enter the reference pipeline, two pipeline levels below where the top-of-stack operators enter the pipeline.

Abstract: A program scanner for a processor having multiple internal streams of instruction and data flow scans a sequence of incoming codes, and employs a plurality of rams to detect various types of syllables in that code. The contents of these rams are signals indicating the various types of codes possible with the output of the rams then being multiplexed to provide an output indicating which syllables can be grouped together for transmission to various units of the processor.

Abstract: An address environment storage unit for a stack-oriented data processor for operating in data sets arranged as structured blocks, or nested pushdown stacks. The address environment storage employs a plurality of sets of display registers such that the current set of display registers does not have to be updated each time the processor moves to a different area of data in memory. The programmer only needs to provide a designation of a lexical level in a particular stack and the offset value from the base of the particular activation record in that stack for addition to obtain actual memory address. When the processor executes a procedure enter operator that calls for a new section of memory in which to operate, a display pointer is changed to point to the set of display registers provided for accessing that new area of memory.

Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.

Abstract: A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.

Abstract: A method and apparatus are shown for use in adding electrical connections to existing printed circuit boards. To this end, apparatus in the form of a multilayered pad is provided which has an adhesive layer over at least part of one face which is responsive to heat so that the pad can be bonded by heat to the surface of a printed circuit board. The other face of the pad includes a layer of stainless steel to which nickel wire can be stitched, or welded. A method according to the invention includes cutting a sheet of pads into individual pads, placing a plurality of pads, adhesive side down, on the surface of a printed circuit board, heating the pads to bond them to the board, and stitching (welding) wire to a succession of pads to complete a series of new connections. Some pads include plated-through-holes enabling connections to be completed from the pads to existing circuitry on the boards and to components mounted in the holes by the use of flow soldering techniques.

Abstract: The present disclosure describes an assembly which has particular application in the testing of printed circuit boards. More specifically, the assembly is comprised of an apertured holding plate which is registered with the board under test, and a probe subassembly. The latter includes a body member having a spring-actuated plunger type probe and a hook-like member. In operation, the body member is advanced toward the plate and the probe and hook-like member enter respective plate apertures. As electrical contact is made by the probe with a desired test location on the board, the hook-like member locks the body onto the plate. The body member is so formed that subsequent pressure applied thereto will release it from its locked condition.

Abstract: A parallel register-transfer mechanism and control section have been disclosed above for use in a reduction process for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.

Abstract: An integrated circuit package for high density applications comprises spring contacts on one face thereof for its removable mounting onto a printed circuit board, the mounting being accomplished by means of a frame assembly and the package being automatically fabricable in a continuous flow process involving its assembly on a transport tape and its final cutting therefrom.

Abstract: In a stop-and-display station in document-handling equipment wherein a document in a track is stopped and viewed through a transparent first wall, whereagainst it is supported by a non-transparent second wall, a reflective photosensor assembly is angled relative to the back wall such that a light beam from a light-emitting diode cannot be specularly reflected onto a phototransistor either from a document or from the inner surface of the transparent first wall. The phototransistor intercepts a portion of the scatter-reflected light from the document. The light from the light-emitting diode is modulated with a predetermined frequency, and the output signal from the phototransistor is filtered by a band-pass filter before threshold detection to provide indication of the presence of a document. A turn-off delay circuit prevents loss of indication of the presence of a document unless signals from the phototransistor have been absent for longer than a predetermined period.

Abstract: The present disclosure describes a connector system for making electrical connections between connectors disposed at opposite extremities of a logic board to conductors in a respective pair of parallel, spaced-apart backplanes. Movable pin headers containing respective pluralities of pins are disposed on the outer surfaces of the backplanes. The pin headers are capable of assuming either a retracted or an extended position. In the former, the pins offer no interference to the insertion or removal of the logic board between the backplanes. In the latter, the pins traverse both feed-through holes in the backplanes and feed-through socket affixed to the opposed interior surfaces of the respective backplanes to electrically engage the connectors of the logic board, thereby completing circuit paths between the respective backplanes and the logic board.

Abstract: A circuit for monitoring the status of electrical signals, such as those present on the control and data lines of an RS-232 interface, includes a single operational amplifier and a dual-color LED indicator. The electrical characteristics of the LED's form a significant part of the circuit parameters. The monitor design provides a predetermined circuit input impedance and positive/negative switching thresholds to effect the selective illumination of the LED's.

Abstract: The present disclosure describes an elongated, articulated gasket assembly which finds particular application in the EMI/RFI shielding of the gaps between adjacent panels of a metal cabinet, such as that used in a mainframe computer. The gasket assembly is characterized by its double-action capability, that is, it may be wiped in either direction under a compressive force, without sustaining any damage. Likewise, the gasket assembly exhibits excellent durability during the routine handling of the panels. Finally, since installation of the present gasket assembly does not restrict movement of the panels, a desired panel may be removed during service procedures without affecting any other panel.

Abstract: A graphic control system under the control of a host processor to display, on a display monitor, high resolution color graphic images. The graphic control system employs a plurality of graphic display controllers each accessing, in parallel, a separate bit map storage area or a plane. When a gray-scale or color display is required, respective planes are read out in parallel and converted for serial transmission with respective outputs being supplied in parallel as a code to a look-up table of color or gray-scale codes that in turn are supplied to a digital-to-analog converter that drives the display monitor. In addition, a compare circuit is provided to receive outputs sent from the respective bit plane stores for comparison with preset outputs from the host computer to determine when the display monitor has reached a boundary of a figure being filled with a particular color or pattern.

Abstract: A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.

Abstract: The present disclosure describes an air sampling system which is particularly effective in detecting minute quantities of smoke caused by electrical short circuits in equipment housed in an air cooled cabinet. More, specifically, the system is useful where large number of rack-mounted printed circuit cards are employed. The system employs air sampling cylinders mounted in proximity to the cards, and through the establishment of a pressure differential, causes an air sample to be drawn into the tubes and through a detector box which includes a smoke detection unit. The presence of smoke is conveyed to a control box which responds by removing electrical power to the cards, thereby averting further damage to the cards or surrounding structures.