Abstract: The present disclosure describes test coupons having predetermined respective test patterns, formed in a multilayer printed circuit board simultaneously with the fabrication of the latter. The test coupons are probed with conventional electrical instruments to provide information as to the occurrence of a misregistration of any given subsurface printed plane or trace, whether or not the misregistration exceeds a specified limit, and if desired, a measure of the degree of misregistration. The foregoing are readily accomplished in a time and cost efficient manner without the need for cross-sectioning portions of the board and the visual observation of the subsurface printed layers.

Abstract: A device for handling electronic circuit components, such as integrated circuit packages, and for facilitating the insertion of the pins or leads thereof into corresponding apertures of a printed circuit board. More specifically, an integrated circuit package assembly may comprise a mounted integrated circuit chip, a block-like multi-apertured element for protecting the package leads, and a heat sink member. The present tool, under operation control, captivates the entire package assembly, ejects the protective block prior to package insertion, positions the assembly on the printed circuit board, and inserts the package leads into homologous apertures of the board--the foregoing requiring minimal, if any, physical contact with the assembly by the operator.

Abstract: This disclosure relates to a network of reduction processors for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.

Abstract: The present disclosure describes a system for substantially eliminating clock signal timing errors occurring between the signal paths of the various cabinets or modules of a large, high speed digital synchronous data processor. Such errors result from the most part because of the long cable lengths needed for coupling the cabinets to a master clock source. The present system provides a measure of the signal delay from the output of the master clock source through the elements of a given cabinet and permits corrective measures to be made at a single location within the cabinet without the necessity of accessing the large number of elements contained therein.

Abstract: Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

Abstract: Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1, is a network 11'0 interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

Abstract: This disclosure relates to a flexible mounting support for a wafer scale integrated circuit system which is adapted not only to support the wafer for maximum cooling exposure but also to contain the necessary driver circuits for the transmission of signals and power between the wafer and the outside world. The mounting support is formed of a plurality of layers with apertures to receive the wafer, which layers are laminated together with certain of the layers being provided with various portions of the lead circuitry required for signal and power transmission between the wafer and the driver circuits and between the driver circuits and the outside world. In particular, this laminated layer mounting support is provided with a mounting layer of a very thin, flexible material and a slightly smaller aperture so that the wafer may be seated thereon and also make electrical contact as may be required for reverse biasing and the like.

Abstract: A four way selector switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less.

Abstract: A five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

Abstract: Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12', exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

Abstract: A four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less.

Abstract: A high speed interconnect network for a relatively large number of processors from as few as five to a hundred or more where the information transfers are serial-by-byte in a time multiplexed manner so that when one or more processors is ready to transmit, there will be an information byte being transmitted every clock time. A bus arbiter controls access to a local bus in a round-robin fashion when one or more than one processor is requesting access to the local bus. The bus arbiter also serves for connection to an overall global loop of bus arbiters each of which has a local bus and a plurality of individual processors.

Abstract: A mechanism for a data processor that is adapted to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so that they may be separately and concurrently executed by a plurality of processing elements. The mechanism makes all memory accesses required by the various tasks and stores those tasks along with corresponding pointers or references to local memory in which the various data items have now been stored. The mechanism employs a symbol translation table in which the tasks are stored in forms of queues along with symbols representing the various references or pointers to local memory. In this manner, various data items can be assigned different symbols or symbolic names for use with different tasks thus further limiting dependency between various tasks and controlling data changes.

Abstract: A data processor having a plurality of processing elements and a mechanism to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so that they may be separately and concurrently executed by the plurality of processing elements. The mechanism makes all memory accesses required by the various tasks and stores those tasks along with corresponding pointers or references to local memory in which the various data items have now been stored. The mechanism employs a symbol translation table in which the tasks are stored in forms of queues along with symbols representing the various references or pointers to local memory. In this manner, various data items can be assigned different symbols or symbolic names for use with different tasks thus further limiting dependency between various tasks and controlling data changes.

Abstract: The present disclosure describes an electronic system for use with low cost audio tape recorders whereby a substantially noise-free wide dynamic range is provided for the recording of analog signals in the DC to 30HZ frequency band. In achieving this result, the system utilizes two FM carrier oscillators having center frequencies displaced from each other and modulated respectively in opposite senses by the signal being recorded. The system also provides an additional utility channel of limited dynamic range for the concurrent recording of time markers, digital signals and the like.

Abstract: The present disclosure describes the fabrication of subminiature electronic devices incorporating conventional integrated circuit (IC) chips or dies. The IC assembly which may be advantageously realized by tape automated bonding processes utilizes an etched double metal clad plastic carrier which allows the chip to be mounted directly to a metallic base formed on one surface of the carrier and to have its signal pads wire bonded to a metallic lead frame disposed on the opposite surface thereof.

Abstract: A mechanism for a data processor that is adapted to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so that they may be separately executed. The mechanism makes all memory accesses required by the various tasks and stores those tasks along with corresponding pointers or references to local memory in which the various data items have now been stored. The mechanism employs a symbol translation table in which the tasks are stored in forms of queues along with symbols representing the various references or pointers to local memory. In this manner, various data items can be assigned different symbols or symbolic names for use with different tasks thus further limiting dependency between various tasks and controlling data changes.

Abstract: This disclosure relates to a reduction processor for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.

Abstract: In a named-data hierarchical memory system wherein data is stored in pages at each memory level, a word valid bit to indicate the presence of data and a word modified bit is appended to each data word and associated detection and control apparatus is provided to permit the page oriented data to be stored and fetched on a word basis at each memory level. The detection and control logic functions to store only the data words in a page which contain actual data and to operate each level as a storage queue for the next lower level thereby eliminating the requirement and associated time delay of prefetching a page from the lower level before storage of any data words therein at the higher level.

Abstract: This disclosure relates to a variable pulsewidth gated clock generator which is able to provide output clock signals with the same rise rate as an external driving clock with the output signal being varied in duration according to logic conditions within the integrated circuit. The circuit of the present invention as disclosed includes a latch which is set by the first phase of a two-phase clock to set the internal logic of the circuit to generate a large output signal during the second phase of the two-phase clock.