Abstract: A circulating shift register memory, particularly adaptable to charge coupled device technology, wherein a plurality of circulating shift registers are arranged to provide a matrix of data bits accessible at a common data front. Address counter circuitry cooperating with the register clocking circuits selects a particular bit location on the data front for each shift of the shift registers. Depending upon a mode signal and beginning address from a host system, the address counter circuitry provides successive accesses in predetermined patterns, for example along a row, column or diagonal of the bit matrix.

Abstract: A speed independent selection switch designed for pipelined message transmission through digital communication networks. The selector routes a message from the input path to one of the two output paths selected by the first bit of the message, that bit then being discarded. Communication paths require four wires.

Abstract: An assemblage of digital devices, each having serial asynchronous input and output channels, can be connected via networks of speed independent arbiter and selector switches. Certain classes of networks have desirable properties: distributed control of routing, conflict resolution, automatic identification of source network address with respect to destination, and exploitation of permissable concurrent operations.

Abstract: A speed independent selection switch designed for pipelined message transmission through digital communication networks. The selector routes a message from the input path to one of the two output paths selected by the first bit of the message, that designed bit then being discarded. Communication paths require four wires.

Abstract: This disclosure relates to a color video system that is adapted to receive digital codes representing values of different colors that are to be displayed to create an image on a standard video monitor. The system employs a video synthesizer which includes a memory in which appropriate digital signals are stored representing the desired transformations of the signals to signals that are to be transmitted to the video monitor. Specifically, the system is adapted to transform respective color codes to codes required for the I, Q, and Y mode of transmission.

Abstract: This disclosure relates to a digital video display system wherein a control element is provided that includes position and count registers to specify the initial position of a scan line and the number of scan lines displayed which registers are supplied with incoming data to specify the position of each character line so that the position of a character image on display can be adjusted upwardly or downwardly to give the appearance of smooth scrolling.The various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image.

Abstract: A speed independent arbitration switch designed for pipelined message transmission through digital communication networks. The arbiter routes a message from one of two input paths to the output path and appends a bit to the message indicating the input path. When requests are present on both input paths, the arbiter accepts messages from them alternatively, choosing the first randomly if the requests arrive simultaneously.

Abstract: A method of fabricating an integrated circuit having a plurality of different devices, which method employs a single mask to define the active areas of all such devices. A silicon oxide-silicon nitride layer is formed on the surface of a silicon wafer so as to define the location of subsequent oxide insulating layers which in turn actually define all the active areas of the circuit. Respective active areas for the different devices can then be formed by selective ion implantation.

Abstract: A method for batch processing wafers by liquid phase epitaxy (LPE) dipping methods for uniformity of film thickness wafer-to-wafer and uniformity of film on each individual wafer for use in bubble (domain) memories comprising, supporting a plurality of wafers substantially horizontal on a substrate holder and lowering and immersing said wafers into the melt to be deposited as a thin film on each wafer and, while immersed, continually moving the wafers up and down as well as continually oscillating the wafers through substantially 360.degree..

Abstract: A speed independent selection switch designed for pipelined message transmission through digital communication networks. The selector routes a message from the input path to one of two output paths selected by the first bit of the message, that bit then being discarded.

Abstract: An extrusion mold for growing crystalline silicon in any desired size at a very high purity level. The mold is formed of molybdenum with any desired width, length and depth. The major portion of its length is immersed in a temperature-controlled environment. A high temperature receiving end of the mold is located in a controlled atmosphere containing an inert gas such as nitrogen. Molten silicon is poured from a crucible into the open end of the mold in the controlled atmosphere. The extrusion mold is at an incline to permit the molten silicon to flow through the mold until it contacts a seed crystal of silicon. The seed crystal is located at the point where the silicon solidifies. The molten silicon begins to form a crystalline structure oriented according to the seed crystal. As crystallization takes place, the seed is slowly pulled out of the other end of the extrusion mold which is open to the atmosphere bringing the crystalline silicon structure with it.

Abstract: This disclosure relates to a V-MOS field effect transistor which is provided with enhanced source capacitance to provide a single transistor dynamic memory cell. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor.

Abstract: A structure for a low-pressure chemical vapor deposition system which achieves greater uniformity of deposition. The structure includes injection means designed to provide more uniform distribution of the reactant gases injected into the system, as well as means to control the gas flow across the surfaces of the respective wafers and then the exhaust of those gases from the system. To this end, plenums which run the length of the deposition chamber beneath or to the side of the wafers are provided with openings arranged in a non-uniform manner to achieve this uniform injection. Furthermore, the wafer support or boat is provided with means to disperse concentrations of the reactant gases so as to provide more uniformity of the gas flow across the surfaces of the wafers.

Abstract: This disclosure relates to a thin film amorphous memory cell which can be fabricated upon the surface of a semiconductor substrate in such a manner as to minimize the surface area requirements for each cell thereby increase the packing density of the memory array. Furthermore, since the cell can be fabricated on top of the semiconductor substrate, other active devices can be fabricated in the substrate so as to further increase the packing density of the integrated circuit chip containing memory array or other circuits.The memory cell is formed of a thin film diode of one or more amorphous semiconductor layers that are doped to form either a PN junction diode or, with one such layer, a Schottky diode, and the memory cell includes an amorphous layer of a tellurium based chalcogenide material that may be employed in either a memory mode or a threshold mode so that the memory cell may be operated in either a non-volatile or volatile manner.

Abstract: An MOS compensation circuit for stabilizing the discharge of a timing capacitor including first and second inverter circuits and an interconnecting feedback circuit which effectively compensate for impedance variances in a capacitor-discharging MOS transistor, particularly those impedance variances due to fabrication tolerance dependent parameters.

Abstract: An apparatus for forming an interconnect structure on an integrated circuit chip by employing a single chamber for both the required etching and anodization. It has been discovered that an etchant-electrolyte such as phosphoric acid solution in the ratios of one part phosphoric acid to four parts of water can serve as both an etchant and an electrolyte without causing deterioration of the photoresist pattern representing the interconnect structure.

Abstract: An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "Open" Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

Abstract: Circuitry for use in bubble memory propagation wherein field drive coils receive energy from an energy storage device (capacitor) through a plurality of selectively located and timed switches. A basic digitally controlled switching arrangement is illustrated in matrix form and, in one embodiment, one capacitor with two voltage sources and, in another embodiment, two capacitors and a single voltage source are utilized. Selective timing of the opening and closing of the switches provides a digitally controlled series of 1/2 sine wave current pulses to meet operating requirements for bubble propagation. Additional variations of the selective timing of switch opening and closings are used to elongate the start and stop pulses to provide better operating margins for these events. Field rotation in either clockwise, or counter-clockwise, or a mix of rotational senses is readily achieved under digital control.

Abstract: A defect tolerant lattice file memory having means in the access column for annihilating lattice bubbles in a previously detected defective row thus eliminating an error in the digital information to be extracted from the lattice file. This annihilation means comprises a ladder formed in a conductor overlay located over the access column in which partial current loops may be formed by disconnecting certain selected portions of the ladder. These current loops create a localized magnetic field when the ladder conductor is activated thus annihilating the selected row of bubbles. Thus, lattice file chips found to have defective rows which will not support and maintain lattice bubbles in their desired coded state can now be utilized.

Abstract: A digital-to-analog converter utilizing magnetic domains with particular application to addressing large capacity bubble memory modules economically and with as short a delay as one cycle of rotation of the magnetic in-plane field including a plurality of storage loops and magnetoresistive sensors arranged in bridge networks to produce signals whose amplitude denote a weighted binary digit.