Abstract: Parallel register-transfer mechanism and control section have been disclosed above for use in a reduction processor for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.

Abstract: The present disclosure describes a dry air breather assembly adapted to be readily mountable over the breather ports of devices which are intolerant of intake air having high relative humidities in excess of a predetermined level. Such devices include the Winchester Hard Disk Unit in which the deposition of excess moisture on the read/write heads and magnetic disk media is particularly detrimental. The present assembly includes a unique elongated, low-profile enclosure for the efficient and effective use of a desiccant having a high moisture removal capability at relative humidities above the predetermined level, and low moisture removal capability, below the level.

Abstract: The present invention describes a tester for determining the value of unknown delay lines in the nanosecond and subnanosecond range. The unknown delay line is introduced into the circuit loop of a free-running square wave oscillator previously calibrated to a predetermined frequency. A change in oscillator frequency occurs which is a measure of the value of the delay introduced into the loop by the unknown line. Such delay may be calculated as a function of the calibration and delay line-measured frequencies. The present tester provides measurements with increased accuracy and rapidity over previous measuring techniques.

Abstract: An allocator for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. The allocator scans selected groups of storage locations in parallel to see if there are any unused storage locations and then places the addresses of those unused storage locations in a queue for use by the processor.

Abstract: A controller for communication between the auxiliary processor and a cache mechanism in the system interface which communication is to be carried on independently of main memory accesses required to update the cache mechanism in an overlapped manner.

Abstract: The present disclosure describes an antenna which may be collapsed and stored in a compact configuration and readily released from storage to assume a deployed operative state. More specifically, the antenna is a wire member comprised of a straight section and an integral transverse helical spring section. The antenna lends itself to storage about the axis of a right circular cylinder while permitting full deployment parallel to the longitudinal axis of the latter. This arrangement permits the storage of potential energies of torsion and bending respectively in the helical spring and straight portions of the antenna, and permits continuous motion in these planes to effect antenna erection and deployment.

Abstract: A real time graphic processor is disclosed which processes graphic cell specifications on a scan line-by-line basis to generate pixel data. The pixel data from each cell specification is assembled to form a completed scan line of pixel data which is used to modulate a printing element, such as a laser diode. The invented graphic processor contains a special purpose cell specification processor which, in addition to generating the pixel data, modifies the cell specification by substituting new horizontal location and cell height indicator values. The modified graphic cell specification is then recirculated to the cell specification processor memory for processing the next scan line.

Abstract: Disclosed is a processor and method for the real time generation of linear arrays of pixel data. The generated pixel data is used to modulate a laser diode as it scans across a printing medium, thereby producing printed font and logo characters.In accordance with the present invention, the real time processor receives a series of cell specifications on a scan line-by-scan line basis, the cell specifications identifying the font type and placement information. The real-time processor uses this information to access from its font memory a linear array of pixel data corresponding to the identified font type. The accessed pixel data is used to modulate the laser diode as it scans the printing medium line-by-line. Thus, as the laser diode is modulated by the pixel's "ones" and "zeros", it is pulsed "off" and "on", thereby generating pixel dots on the print medium itself or on a photosensitive drum which subsequently prints an image on a page through an electrostatic process.

Abstract: A microcontroller for controlling a digital device which controller is formed of a plurality of control stores each of which is provided with a register counter to address different locations within corresponding control store. Each control store is accessed each clock cycle and an instruction register is provided to receive one of the fetched microinstructions from the selected control store. In this manner, a microinstruction is presented to the instruction register each clock cycle even though the previous microinstruction was a conditional branch, a jump to subroutine or a return to subroutine instruction. In order to accommodate jump to subroutine and corresponding return from subroutine instructions, the respective address of the return subroutine is stored in a push-down stack for presentation to a selected one of the above-referred-to register counters in an order the reverse of the order in which those addresses were placed on the top of the stack.

Abstract: A two-level controller for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. The two-level controller is formed of a hierarchy of two control stores wherein the receipt of a command code by the first control store from the processor causes it to address the second control store. Each control store is provided with program counter means to receive its respective address and to increment that address until it receives a new address so as to asynchronously control simultaneous operation of a memory interface to said memory modules and a cache mechanism coupled to the processor.

Abstract: Workstations may advantageously be interconnected in a cluster arrangement wherein multiple "slave" stations utilize the database which exists in a "master" unit. The cluster interface has been implemented as a wired system but the latter involves significant limitations as to distance between units, electrical noise restricting data transmission rates and the protection of sensitive data from compromise. The fiber optic interface module of the present invention eliminates the foregoing limitations by translating the electrical signals of the wired system into optical signals for transmission and restoring them to electrical signals at a receiving unit.

Abstract: The present disclosure describes an alignment fixture having particular application in surface-mount connector technology. The fixture utilizes a plurality of through-hole connector sections having pins which are retained in holes formed in a plate and which exhibit a predetermined positional tolerance. A plurality of surface-mount connector sections to be mounted adjacently on the edge of a printed circuit board are plugged into mating through-hole connector sections, and positioned with respect to conductive pads on the board surface. In effect, the above-mentioned positional tolerance has been transferred by the fixture to the surface-mount connector sections.

Abstract: This disclosure relates to a programmable unit employing plural levels of sub-instruction sets in addition to conventional instruction sets. The conventional level of instruction sets is employed to specify computational routines and other processing algorithms to be carried out by the unit. Each instruction in a conventional set is implemented in the unit by a sequence of first level sub-instructions which specify the various operations to be carried out within the unit which operations are comprised within the specific routine. In turn, the various first level sub-instructions are implemented by second level sub-instructions which specify the various control signals required to set the various gates as required for the particular unit operation to be carried out. With this hierarchy of sub-instruction sets, first level sub-instruction sets may be interchanged dynamically during the operation of the unit to dynamically change the processing capability of the unit.

Abstract: The present disclosure describes a system for handling detected error signals, providing the circuit elements for processing fault reports and implementing automatic fault isolation. More specifically, the system develops a fault report for each component based upon error signals derived therefrom. Changes in the fault report are detected and selector circuits are actuated to automatically isolate the fault to the particular component or components, or to reset the system in response to previous fault correction. The present system is advantageous in that it is independent of the equipment technology and applies to all design levels, from the unit itself to the individual components of which it is comprised.

Abstract: A microcontroller for controlling a digital device which controller is formed of a plurality of control stores each of which is provided with a register counter to address different locations within corresponding control store. Each control store is accessed each clock cycle and an instruction register is provided to receive one of the fetched microinstructions from the selected control store. In this manner, a microinstruction is presented to the instruction register each clock cycle even though the previous microinstruction was a conditional branch, a jump to subroutine or a return to subroutine instruction. In order to accommodate jump to subroutine and corresponding return from subroutine instructions, the respective address of the return subroutine is stored in a push-down stack for presentation to a selected one of the above-referred-to register counters in an order the reverse of the order in which those addresses were placed on the top of the stack.

Abstract: A microcontroller for controlling a digital device which controller is formed of a plurality of control stores each of which is provided with a register counter to address different locations within corresponding control store. Each control store is accessed each clock cycle and an instruction register is provided to receive one of the fetched microinstructions from the selected control store. In this summer, a microinstruction is presented to the instruction register each clock cycle even though the previous microinstruction was a conditional branch, a jump to subroutine or a return to subroutine instruction. In order to accommodate jump to subroutine and corresponding return from subroutine instructions, the respective address of the return subroutine is stored in a push-down stack for presentation to a selected one of the above-referred-to register counters in an order the reverse of the order in which those addresses were placed on the top of the stack.

Abstract: The present disclosure describes a latch assembly wherein structural members are coupled to each other by an electric match-type device interposed therebetween. The latter device generally comprises a body portion having electrical connections thereto and a rigid mass of combustible material firmly adhered to an extremity thereof. At least a pair of the structural members are individually coupled to the combustible material. Remote activation of the match by the passage of electric current therethrough results in the firing of the combustible material and the consequent opening of the latch through the elimination of the coupling force between the structural members.

Abstract: A metal interconnect structure for an integrated circuit with a layer of refractory metal over the structure to prevent formation of hillocks, thereby eliminating a hard anodization step. The refractory metal may be tantalum, titanium-tungsten alloys, hafnium, or other refractory metals which form insulating anodic oxides.

Abstract: The mounting assembly of the present disclosure finds particular application in shielded electrical cable having connectors at opposite extremities thereof and carrying electrical conductors between spaced-apart equipments having respective mating connectors. In accordance with the disclosure, a mounting assembly is provided which may be disposed at either extremity of the cable, or at both extremities, and which permits the cable connectors to rotate through a prescribed arc about the cable axis. This rotation compensates for the torsional inflexibility of the cable, thereby facilitating the orientation of the mating connectors required for attachment, and electrically linking the equipments.

Abstract: A digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor.