Abstract: This disclosure relates to an electron beam generator and focusing mechanism including a high current thermionic field emission source to establish a high current electron beam and an electro-magnetic focusing means placed along the axis of the electron beam between the source and the target so as to provide a large image focal distance with the electron beam source being formed of a tungsten cathode which is coated with zirconium.

Abstract: A cover layer for flexible circuits which provides increased flexibility. The cover layer encapsulates a flexible circuit having a plurality of spaced conductors on a flexible insulating substrate. The cover layer is a tri-layered laminate having a first layer of insulating film, a second intermediate layer of a thermosetting adhesive, and a third layer of a phenolic resin adhesive. The cover layer is bonded to the flexible circuit with the third layer of phenolic resin adhesive being contiguous the conductors.

Abstract: This disclosure relates to a charge coupled device memory that is content or associative addressable with the respective word locations (loops) being searched concurrently although word access is serial in manner. Data bits in respective word loops are arranged in a staggered manner such that when the first bit of the first word is at its comparison location, the second bit of the second word is at its comparison location and so forth. The comparand and mask bits are shifted serially from comparison location to comparison location and recirculated in synchronism with the recirculation of the word loops. Content addressing logic includes a series of match bit shift registers, one for each comparison location, to record match occurrences. When a word match occurs, the address of the respective word loop is sent to the memory to read out the data bits stored therein.

Abstract: An asynchronous system includes a plurality of cascaded asynchronous cells in which data is transferred through the system according to the presence of data in the cells. Each cell contains two latches for storing binary data. Means are provided for feeding back to the previous cell a signal indicative of data stored in either of the latches. Transfer gate means cooperating with the latches and the feedback data presence signal provides a means by which data is sequentially transferred through the queue according to the presence or absence of data in the cells.

Abstract: A semiconductor device package which can be readily mounted on a printed circuit board without requiring soldering or intermediate connectors. A supporting substrate has a unique lead frame configuration thereon in which the leads extend around side portions of the substrate and form integral spring contacts projecting from the lower surface of the substrate. The package preferably includes a metallic stud having a head portion mounted in the substrate for receiving a semiconductor device and a rod portion extending from the lower surface of the substrate. The rod portion of the stud can be removably secured in an aperture in a printed circuit board to engage the spring contacts with corresponding conductors on the circuit board.

Abstract: A data processing system with virtual memory and the ability to vary the program window size for each program to be processed. The system includes at least one processor, a main memory, a secondary storage and a channel to handle data transfer between the secondary storage and main memory. Each processor is provided with means to measure the processing time of the processor and the data transfer time of the channel for transferring either variable segments or fixed pages from the secondary storage to main memory in response to page faults. A program table is provided in the processor to contain names of pages which reside in main memory for the current program, which table implements a page replacement mechanism such that as new pages are transferred to main memory for the current program, the least recently used pages are removed therefrom.

Abstract: A method of making a multilevel conductor pattern for a semiconductor device. An aluminum layer on the substrate surface provides a situs for first level conductors. Successive soft and hard anodization steps are advantageously used to provide excellent intralevel isolation and interlevel electrical connection in desired areas. First level conductor sites are masked and the two anodized films are selectively removed in the desired nonconductive areas. The remaining first level aluminum is completely anodized. An insulating layer is then deposited and vias are formed therethrough to connect a subsequently deposited second level metallization layer with the conductor sites.

Abstract: A high speed circuit for converting CML/ECL gate signals to TTL gate signals. The circuit includes two parallel current paths coupled to a current mirror section in which uniform current is maintained in portions of each path. Each current path includes a transistor which is coupled to the CML/ECL gate for sensing the differential voltage in the gate. The TTL gate is coupled to one of the current paths which steer current into or out of the TTL gate depending upon the differential voltage sensed in the CML/ECL gate.

Abstract: A fixture for holding a semiconductor wafer during anodization. The fixture has a major surface with a plurality of concentric ridges on the surface for supporting a semiconductor wafer, with adjacent ridges defining concentric channels therebetween. The fixture includes electrical contact means for contacting the inward surface of the wafer. At least one channel surrounds the contact and an insulating fluid is circulated in the channel to prevent the anodizing solution from electrically shorting to the contact. Means are also supplied for maintaining a vacuum in another channel to secure the wafer against the ridges of the fixture.

Abstract: A system for driving display panels includes a plurality of MOS integrated circuit chips for each character row in the display panel. Current level control means are provided by the present invention to maintain uniform brightness in all of the character display rows regardless of varying characteristics between the chips driving each row.

Abstract: This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective columns by source followers and leads from the latch drive write back gates coupled to the respective columns so as to restore a "zero" level of a cell and also leave a precharged "one" level with the cell by charging the appropriate column. The respective columns are initially precharged and balanced and then driven by negative going signals.

Abstract: This disclosure relates to a storage system employing a serial periodic memory as the storage mechanism. The storage mechanism has one or more control and access ports which control data transmission to and from the storage mechanism, each port including input and output devices associated with a data track of the storage mechanism. A queue shift register is coupled between the input and output devices to receive previously stored information characters which are to be temporarily held when newly received information characters are to be written into the storage media. Control of the system resides in the control ports and is activated by commands from the external sources. A character set is employed which includes a beginning delimiter character and an ending delimiter character such that information segments may be of any length up to the capacity of the storage mechanism.

Abstract: A flexible circuit assembly and a method of making it in which there are no separate electrical interconnections between the flexible interconnecting cable and the rigid connector. A flexible insulating film is bonded to a surface of the connector member and extends from the connector to provide a flexible interconnecting cable for external electrical connections. A plurality of conductors on the insulating film provides a continuous electrically conductive path thus providing an interfaceless electrical connection between the rigid connector and the flexible interconnecting cable. In the method, a metallic clad insulating film is placed on a surface of a rigid support member which includes a portion which will serve as the connector. The support member also includes a filler block portion in the space designated for the flexible interconnecting cable. The film is selectively bonded to the connector portion of the support member. Conductors are then formed on the insulating film.

Abstract: This disclosure relates to memory array organization of single transistor cells and the differential sense amplifiers provided therewith. To accommodate the differential sense amplifiers, the array is laid out in rows and functional columns where a functional column consists of a pair of columns such that odd row cells are connected to the odd column of the pair and even row cells are connected to the even column of the pair. A differential sense amplifier is then provided for each pair of odd and even columns which are inherently balanced at the sense amplifier terminals. Single ended or edge ended I/O circuitry is provided with direct access to the respective pairs of columns.

Abstract: A peripheral interrupt priority technique in a micro program system is disclosed which system employs two levels of subinstruction sets. The first level of subinstructions, or micro instructions, is implemented by a second level of control instructions that can be stored in a processor read-only memory. The respective micro instructions are made up of varying numbers of syllables according to the function of the particular micro instructions. The various types of micro instruction syllables are stored in a micro instruction memory to be fetched therefrom in sequence in accordance with the requirements of a particular macro instruction or subject instruction. In this manner, a variety of micro instructions can be created by selecting a plurality of different syllables from the micro instruction memory. A different control instruction syllable is provided to specify each combination of the function to be performed and the source and destination registers to be used with the particular buses in the processor.

Abstract: A semiconductor device package and a method of making it. A woven fiber mat impregnated with an epoxy adhesive serves as a first housing member. It includes an opening therein for receiving a semiconductor device. The housing member is placed on a supporting heat sink and a lead frame placed on top of the housing member. This subassembly is heated to bond the elements together by curing the epoxy adhesive in the first housing member. A similar second housing member is then placed over the lead frame. The second housing member includes an opening therein which is slightly larger than the opening in the first housing member. A lid is placed on top of the second housing member to cover the opening after the semiconductor device has been bonded to the substrate within the openings in the housing members. The assembly is then again heated to bond the remaining elements together with the epoxy adhesive in the second housing member to form a completed package.

Abstract: A unique contact pin configuration for an electrical connector provides an advantageous connection with a leadless semiconductor device package and a printed circuit board on which the connector is to be mounted. Each contact pin includes an elongated shaft portion, a resilient contact portion and a crossbar portion which offsets the contact portion from the shaft portion of the contact pin. Each contact pin is alternately situated 180.degree. in cavities disposed on two opposed sides of the connector. Consequently, the contact portions of the contact pins provide internal electrical connection to a leadless semiconductor device package with a small contact pad spacing, while providing an external electrical connection via the contact pin shaft portions with a larger spacing therebetween. Also described herein are distinctive stand-off bumps which are coaxial with the shaft portions of the contact pins to insure level mounting onto a printed circuit board.

Abstract: An MOS integrated circuit chip for both addressing and driving display devices in display panels. The chip includes low-level logic devices for receiving and manipulating data for energizing a selected number of devices in the display panel. An output driver portion is coupled to the display devices and energizes the devices in response to the data received by the input logic. The output driver portion includes a transistor in which the drain region extends deeper into the substrate than the source region of the transistor, as well as the remainder of the active regions in the integrated circuit chip. Accordingly, the integrated circuit chip can withstand a high breakdown voltage at its driver output, while also providing high density logic devices thereby minimizing discrete components and their associated separate electrical interconnections.

Abstract: A semiconductor device package which can be readily mounted on a printed circuit board without requiring soldering or intermediate connectors. A supporting substrate has a unique lead frame configuration thereon in which the leads extend around side portions of the substrate and form integral spring contacts projecting from the lower surface of the substrate. The package preferably includes a metallic stud having a head portion mounted in the substrate for receiving a semiconductor device and a rod portion extending from the lower surface of the substrate. The rod portion of the stud can be removably secured in an aperture in a printed circuit board to engage the spring contacts with corresponding conductors on the circuit board.

Abstract: This disclosure relates to a programmable unit employing plural levels of sub-instruction sets in addition to conventional instruction sets. The conventional level of instruction sets is employed to specify computational routines and other processing algorithms to be carried out by the unit. Each instruction in a conventional set is implemented in the unit by a sequence of first level sub-instructions which specify the various operations to be carried out within the unit which operations are comprised within the specific routine. In turn, the various first level sub-instructions are implemented by second level sub-instructions which specify the various control signals required to set the various gates as required for the particular unit operation to be carried out. With this hierarchy of sub-instruction sets, first level sub-instruction sets may be interchanged dynamically during the operation of the unit to dynamically change the processing capability of the unit.