Abstract: This disclosure relates to an electrically alterable amorphous memory device which can be switched from a high resistance state to a low resistance state, which device has a stable voltage threshold that is temperature insensitive throughout the lifetime of the device. The memory device is formed of a graded structure having at least three regions or layers of amorphous material selected from the tellurium based chalcogenide class of materials, particularly tellurium-germanium systems. The center or middle region is formed of the eutectic material which is in the range of 15 to 17 percent germanium although this range may vary from 10 to 25 percent. The top region or the region closest to the positive electrode is primarily tellurium with from 0 to 10 percent germanium.

Abstract: A method for chemically treating a single side of a workpiece, such as for etching or anodizing a semiconductor wafer, comprising, placing such a workpiece face down on a flat centrally apertured, relatively level table having a top or work surface of a size and shape commensurate with the dimensions of the workpiece and introducing the liquid for the chemical treatment between the top surface and side of the workpiece to be treated where the liquid passes over the entire surface to be treated and then returns to its source. The method also includes, for certain applications, a pre-processing of the workpiece by oxidizing the workpiece surface on the side of the workpiece opposite of the one to be treated to be treated to prevent creeping of the liquid around the edges thereof.

Abstract: A package having bubble memory components comprising an innerassembly of bubble memory chips surrounded by spaced orthogonally oriented drive coils, a printed circuit board having a rigid support portion for the chips and a flexible portion containing conductors for direct interchip communication and for direct connection to the outside world, means in the form of tapers of controlled thermally conductive material for assisting in controlling the temperatures of the bias magnets and for providing a magnetic gradient for bubble propagation, thermal compliant members, and flexible heat conductors which together with the tapers, manage the heat within the package.

Abstract: A method for forming an aluminum interconnect structure on an integrated circuit chip which method employs the anodization of the aluminum but eliminates the necessity for the formation of a hard anodic barrier on the aluminum. Furthermore, the technique provides a superior "cold via" contact. A layer of molybdenum is deposited over the aluminum conductive layer which molybdenum layer is not as wide as the desired interconnect structure and then covered with a dielectric which is patterned to the same width as the desired interconnect structure so as to protect the molybdenum from attack by an electrolyte. Anodization can then be performed to achieve the interconnect structure and a via is etched in the dielectric.

Abstract: In a bubble memory system having a detector device for sensing the presence or absence of magnetic bubbles in a bubble stream and producing an output signal accordingly which is sensed by a differential sense amplifier having a clamp circuit to select the voltage level with which the signal is to be compared at a sampling time and a strobe circuit for sampling the signal at the preselected time, a dynamic input signal offset for enhancing the signal-to-noise factor at the input to the sense amplifier so that a signal representing an absence of a bubble is clearly distinguishable over a bubble presence signal. This invention disclosed is disclosed as operable with a d.phi./dt or magnetoresistive bridge type detectors and comprises means for shifting the signal level negatively by providing a negative going pulse just after the time the clamp circuit is released and while the signal is being sampled.

Abstract: A method for forming an aluminum interconnect structure on an integrated circuit chip which method employs the anodization of the aluminum but eliminates the necessity for the formation of a hard anodic barrier on the aluminum. Furthermore, the technique provides a superior "cold via" contact. A layer of tantalum is placed over an aluminum layer which tantalum is patterned to define the desired aluminum interconnect structure. Both the exposed aluminum and the tantalum are anodized to form both the interconnect structure and a thin layer of anodic tantalum which is then removed.

Abstract: This disclosure relates to a digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: An I/O data interface provides an access mechanism without requiring additional lines on the bus for device address presentation for the request of access. Each peripheral device can detect an invitation-to-request access signal and in response thereto, to supply its own device address on the bus in a serial manner with any other device requesting access. Respective device addresses are assigned to respective peripheral devices in accordance with their priority, the higher priority devices having a higher address and the lower priority devices having a lower address. If any address bit of a particular device is lower than an address bit on the bus, the device ceases to supply its address bits with the result that only the requesting device having the larger device address will be selected for communication over the I/O bus.

Abstract: A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e., not connected to any other conductor, may be located within a shot distance, i.e., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories.

Abstract: A duplex driver/receiver module having circuitry which permits the sending and receiving of data from an identical module simultaneously, utilizing resistive and gating techniques to overcome differential noise, to accommodate circuit manufacture process variations and transmission line resistances within the CML logic environment.

Abstract: In a bubble memory system having storage loop architecture, means for buffering both read and write requests in order to improve performance including, in the embodiment disclosed, two sets of short or buffer loops, one for the write section and one for the read section, which are virtually asynchronous with respect to each other and to the main memory storage loops and in which data may be temporarily stored prior to transfer into the main storage loops or prior to transfer into an output track.

Abstract: An associative magnetic domain memory comprising; a predetermined number of storage loops having a predetermined number of magnetic elements on which domains circulate, said domains or absence of said domains on said magnetic elements in said storage loops representing bits of binary information; write-in section and read-out means disposed relative to said storage loops; said write-in section including, generator for generating bits and propagating said bits to positions adjacent said storage loops as a set of bits with a subset of said bits representing address bits and the rest of said set being data bits, and a gate for transferring said set of bits into said storage loops for storage therein; said read-out section including a replicator for forming replicas of sets of bits in said storage loops, a gate for transferring said replica sets one at a time, a sensor for receiving and sensing said transferred replica sets if one of said address bits does not match the desired address criteria.

Abstract: The method of manufacture of the present invention provides a wafer that is better than a bulk monocrystalline silicon wafer and equivalent to silicon on sapphire (SOS) wafers for use as substrates for integrated circuits. The method comprises taking an inexpensive slab of silicon having <111> crystal orientation and by low pressure CVD, high pressure CVD, or plasma deposition techniques depositing a polycrystalline layer of sapphire on the <111> silicon base. The polycrystalline layer of sapphire is then annealed at an elevated temperature to form a monocrystalline layer having a <1101> orientation. A single crystalline layer of silicon having <111> crystal orientation is then epitaxially grown on the sapphire. The resultant multilayer wafer is equivalent in function and reliability to a silicon on sapphire wafer without the commensurate cost.

Abstract: A method for forming an interconnect structure on an integrated circuit chip by employing a single chamber for both the required etching and anodization. It has been discovered that an etchant-electrolyte such as phosphoric acid solution in the ratios of one part phosphoric acid to four parts of water can serve as both an etchant and an electrolyte without causing deterioration of the photoresist pattern representing the interconnect structure.

Abstract: An EFL D-type latch having both true and complement output with a data input transistor and a bistable storage cell comprising first and second transistors, at least one of which is multi-emitter, connected such that the true output is connected to the collector of the first transistor of the storage cell and the complement output is connected to the collector of the data input transistor and the second transistor of the storage cell to take advantage of the phase inversion of the latter transistors depending upon which one of these transistors has current flowing therethrough. Also described is an EFL type complement output circuit connected as a D-type master-slave flip-flop, an RS latch, and a JK master-slave flip-flop using an RS master latch and a D-type slave latch. Also disclosed is a toggle flip-flop implemented with a D-type flip-flop to complete an EFL type logic family.

Abstract: A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e., not connected to any other conductor, may be located within a short distance, i.e., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories.

Abstract: In a bubble memory system having storage loop architecture, means for decoupling the write-in means and the read-out means from the propagation cycle of the storage loops so that data may be transferred in and out of said storage loops independently of each other and of the propagation cycle thus decreasing the access time of a bubble memory.

Abstract: An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps.

Abstract: A semiconductor device package and a method of making it. A woven fiber mat impregnated with an epoxy adhesive serves as a first housing member. It includes an opening therein for receiving a semiconductor device. The housing member is placed on a supporting heat sink and a lead frame placed on top of the housing member. This subassembly is heated to bond the elements together by curing the epoxy adhesive in the first housing member. A similar second housing member is then placed over the lead frame. The second housing member includes an opening therein which is slightly larger than the opening in the first housing member. A lid is placed on top of the second housing member to cover the opening after the semiconductor device has been bonded to the substrate within the openings in the housing members. The assembly is then again heated to bond the remaining elements together with the epoxy adhesive in the second housing member to form a completed package.