Abstract: Apparatus for serially programming a microcontroller's on-chip EPROM includes mode decode logic that responds to operating mode input signals by generating corresponding operating mode signals, including an EPROM mode signal. An upper byte address shift register serially receives a most significant address portion of an EPROM address in response to a shift clock signal and provides the most significant address portion as an upper byte parallel output. A lower byte address shift register serially receives a least significant address portion of the EPROM address in response to the shift clock and provides the least significant address portion as a lower byte parallel output. A memory address register loads the upper and lower byte parallel outputs from the upper and lower byte address shift registers, respectively, and provides an EPROM address output in response to a load signal. An EPROM memory element responds to the EPROM address by providing access to a storage element specified by the EPROM address.
Abstract: A method of extracting an impurity profile from a diced semiconductor chip having cellular construction. The cells are arranged in a matrix the columns and rows of which have a defined column pitch a.sub.x and a defined row spacing a.sub.y. In accordance with the method, the diced chip is bevelled from its original surface to expose the cells. The two probes of a Spreading Resistance Profile (SRP) device are then placed in contact with the dopant regions of two cells in the same row of the matrix, the distance .DELTA.X between the probes being ma.sub.x, where m is an integer, and the total resistance R.sub.T between the probes is measured. The SRP device is then stepped through a plurality of rows in the matrix, contacting cells in the same two columns as in the case of the first measurement, thereby interactively generating a plurality of total resistance R.sub.T measurements. The total resistance R.sub.T measurements are then combined to obtain the doping profile of the dopant region.
Abstract: An integrated circuit includes a plurality of circuit elements interconnected to operate as a circuit and formed in a common semiconductor substrate. The substrate is mounted on a supporting package, resulting in a mechanical stress in the substrate which is symmetrical about at least one given axis. At least the circuit elements with operating characteristics which are altered by the mechanical stress and which have a critical matching or ratio relationship are arranged symmetrically about the stress axis of symmetry. In a preferred form, the integrated circuit is a linear circuit, such as an operational amplifier employing junction field effect transistors (JFETs) for its input stage and bipolar transistors for its amplifier stage. Providing device symmetry about an axis of mechanical stress symmetry enables shifts in input offset voltage for such operational amplifiers to be reduced up to a factor of about 10.
Abstract: A system for electroplating metals, such as tin and solder on semiconductor lead frame strips includes a magazine for carrying the lead frames and a separate plating rack for carrying the magazines. The plating rack, which has an insulated surface, includes means for directing a current to the lead frame strips when the magazine is inserted in the plating rack. An electric coupling means is also provided for assuring that the current from the plating rack is evenly distributed among the individual lead frame strips so that uniform plating results. The magazine is suitable for transporting and storing the lead frame strips during assembly of semiconductor components, and it is unnecessary to remove the lead frame strips from the magazine for mounting on the plating rack.
Abstract: A metal resistor having a positive temperature coefficient of resistance is connected to a current source to develop a voltage drop that acts as an offset for a .DELTA.V.sub.BE differential amplifier. Since this offset voltage has a positive temperature coefficient it will compensate the resistor coefficient to develop a constant current. The constant current can be employed in a current sink sense-shutoff combination or it can be used to develop a plural output current source/sink combination.
Abstract: A heat exchanger for cryogenic liquid evaporation is shown. A coil of tubing is coupled to the source of cryogenic liquid and heated by the flow of water. The other end of the coil is the gas exit at about atmospheric pressure. The gas back pressure in the coil is employed to self regulate the flow of cryogenic liquid into the heat exchanger.
Abstract: A voltage controlled oscillator circuit is disclosed. A CMOS circuit version is detailed. A relaxation oscillator has its input coupled by way of a voltage follower buffer to the input terminal where the control voltage is applied. The operating frequency is determined by the circuit resistor and capacitor values along with the control potential. A linear frequency versus voltage response is obtained and the circuit will operate at low supply voltages.
Abstract: A method for solder plating metal leads in plastic semiconductor packages comprises cleaning the leads followed by electroplating tin or a tin/lead alloy onto the leads. The cleaning is effected with a non-corrosive solution which is either a carboxylic acid, a hydroxycarboxylic acid, or a combination of both. The electroplating solution is a sulfonic acid or citric acid based system, including suitable tin salts and/or lead salts. A sequestering agent may be used to inhibit the corrosive effect of the electroplating bath.
June 3, 1985
Date of Patent:
May 20, 1986
National Semiconductor Corporation
Vijay M. Sajja, Ranjan Mathew, Jagdish Belane
Abstract: A high capacitance/low leakage capacitor for use in a dynamic RAM cell fabricated from a metal silicide or metal silicide/poly capacitor plate structure, with formation of an anodic metal/silicon/oxygen insulating film over that structure.
Abstract: A low noise oscillator is described suitable for use in an AM stereo radio receiver. The oscillator circuit includes means for controlling its amplitude at a constant low level. The oscillator is amenable to electronic tuning and IC construction.
Abstract: A class B IC transistor output stage, using a pair of NPN transistors, is described. A quasi-complementary transistor is employed to establish the stage quiescent bias. An NPN bias transistor is coupled to the output sink transistor and is driven from the emitter of the input driver transistor. Therefore, the input signal is coupled to apply the signal directly to the base of the sink transistor as well as to the source transistor. This feedforward arrangement by-passes the PNP transistor when a signal is applied so that the asymmetrical performance of the PNP transistor does not adversely affect the signal performance.
Abstract: A class AB monolithic silicon IC output stage is shown wherein the main output transistors are NPN structures. The current sourcing transistor is provided with an additional scaled down reference emitter and the two emitters connected to the inputs of an op amp which has its output coupled to drive the current sink transistor. The base of the current source transistor is driven from a high gain driver transistor stage which may also contain a d-c level shifter that permits the inclusion of a complementary current sink transistor that can greatly reduce cross-over distortion while conducting only quiescent current.
Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.
November 9, 1983
Date of Patent:
April 22, 1986
National Semiconductor Corporation
Hee Wong, Ramanatha V. Balakrishnan, Herb O. Schneider
Abstract: The plating apparatus (10) includes a pair of loop belts (20,21) rotating on two sets of pulleys, each set of pulleys including pulleys (11,12), to drive a strip (40) to be stripe plated past a translatingly movable electrolyte manifold (41) containing a series of electrolyte inlet and outlet slots (70,71) in its strip-facing surface. Electrolyte is sprayed from the inlet slots through apertures (24) in a back-up layer of at least one of the belts and through a slot (22) formed between belt segments. Vacuum or air pressure inlets (78,96) are provided at the ends of the manifold to prevent egress of electrolyte from the nip between the pairs of belts. One pulley of each set of pulleys is adjustable to tension the belt and an intermediate roller arrangement is included between each of the pulleys in each set to monitor the belt tension and provide sufficient frictional holding contact between the belts and the workpiece strip and desired sliding contact between the belts and the manifold surface.
Abstract: A digital transformation system for converting between logarithm functions and floating point functions very quickly by normalizing the floating point number in the range of one to two, and adapting one function as the other function, after a correction, which correction is generated by a ROM using the one function as an address.
Abstract: A circuit for regulating the internal programming voltage (Vpp) supplied to an integrated circuit memory device. The invention limits the internal programming voltage to a maximum value no greater than the field assisted breakdown voltage of on-chip transistors and/or the field transistor threshold voltage. Representatives of the several different types of transistors provided on an integrated circuit substrate are incorporated into the voltage regulating circuit. The regulator transistors are placed in the circuit in such a way that they are designed to break down first in the event of an excessive internal programming voltage (Vpp). In this way, the regulator transistors limit the voltage sent to the operating circuitry of the integrated circuit.
Abstract: Reduction of the encroachment of a grown field oxide layer during MOS device fabrication by covering a masking anti-oxidant layer that defines the active element area of a semiconductor substrate with a layer of passivation material which extends over the edge of the anti-oxidant layer to contact the pad oxide over the semiconductor substrate surface.
Abstract: A technique for communicating digital data through a noisy medium using phase modulated carrier signals. A multiphase clock drives parallel channels to sample the received signal, avoiding the need for a phase locked loop. Data is recovered from the noisy carrier by a two stage statistical filtering technique and pattern analysis of the filtered signals.
Abstract: An output stage is disclosed wherein class AB bias is employed. The stage is quiescently biased by means of current mirrors so that the bias is controlled mainly by ratioed geometric elements. The output transistors are biased by means of unity gain common gate drivers that provide the desired level shifting. The output voltage can be swung from from close to the rail potential of the source of the n channel output transistor to close to the rail potential of the source of the p channel transistor. The circuit can drive relatively large load currents and can be fabricated using either CMOS or conventional bipolar integrated circuits.