Abstract: A CMOS linear amplifier is disclosed with a frequency compensation circuit that employs a Miller integrater construction in which the feedback capacitor is coupled by way of a noninverting amplifier operating at constant current and therefore does not load the inverting amplifier input or bypass the integrator amplifier.

Abstract: The leads on a VLSI semiconductor package are bent and secured to the package so as to improve their stability. The thin fragile leads are thereby substantially immobilized so that they will not be deformed during post packaging handling and testing.

Abstract: An integrated circuit buffer inverter is created by cascading an emitter follower stage with a common emitter stage. Both stages include constant collector current loads. The emitter follower stage is adaptively biased from a current mirror that is driven from the collector of the emitter follower for the purpose of maximizing bipolar drive to the common emitter stage.

Abstract: A CMOS Class AB power amplifier is disclosed wherein supply-to-supply voltage swings across low resistive loads are efficiently and readily handled. A high gain input stage including a differential amplifier driving a common source amplifier drives unity gain push-pull output stage. Included in the invention is circuitry to control the DC bias current in the output driver devices in the event of an offset between the push-pull unity gain amplifiers.

Abstract: An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.

Abstract: A CMOS gate protection diode clamping the input terminal to substrate potential is prevented from injecting carriers into the substrate and causing SCR latchup by forming the diode as a well to substrate junction, surrounded by another, reverse-biased, well, to both reduce injection and collect parasitic injected carriers before they can diffuse to cause latchup.

Abstract: An improved dynamic MOS RAM having a plurality of selection lines and data lines and a plurality of storage cells connected thereto, wherein each storage cell includes a storage capacitor having first and second plates, wherein the second plate is adapted to be coupled to a reference potential terminal; and a MOSFET having a semiconductor substrate, a gate connected to one of the selection lines, a first conduction terminal coupled to one of the data lines, and a second conduction terminal connected in common with a first plate of the storage capacitor, is disclosed. The first plate of the storage capacitor includes first doped polysilicon conductive layer that has the majority of its area separated from the semiconductor substrate of the MOSFET by at least an insulating layer. The second plate of the storage capacitor includes a second doped polysilicon conductive layer that is at least coextensive with and insulated from the first conductive layer.

Abstract: A digital circuit to approximate the product of two numbers by shifting the bits in one number to higher significance positions by an amount equal to the bit position of the most significant "one" in the other number, useful in digital speech recognition and synthesis.

Abstract: A current limiting circuit, for a serial commutator motor, that monitors the flow of current through resistances chosen to model the motor, rather than the noisy flow of current through the motor itself. Current for one of the modeling resistances is derived from a tachometer on the motor and is thus proportional to motor speed.

Abstract: A tape assembly process attaches semiconductor chips to a tape via thermocompression gang bonding and the tape is wound onto a reel. The tape is fabricated during its manufacture to have a plurality of spaced finger array patterns. The inner finger ends are located so as to mate with the bonding pads of a semiconductor device and are bonded thereto. A ring-shaped strip is included in each finger pattern that joins all of the fingers in each pattern into a unitary structure in which the fingers are accurately spaced. Where the ring joins onto the fingers, weakened regions are introduced and the side of the tape that contains the semiconductor device includes a recess that is in registry with the ring. A ceramic substrate that will ultimately mount the semiconductor device is provided with an array of conductor patterns that match the tape finger patterns. A layer of sealing glass is screened over the ceramic, so as to align with the ring.

Abstract: An improved method to calculate the relative position between a plating head and an intermittently moved web of material that is to be plated wherein a nozzle directs pressurized fluid through an aperture in the web and the back pressure is monitored as an indication of the relative position of the nozzle and the aperture. Back pressure is represented digitally and a microprocessor waits an interval for the pressure to stabilize, compares the digital signal to a look up table in memory to determine the error in position, and commands movement of the plating head a distance sufficient to bring the error to zero.

Abstract: An emitter coupled oscillator having a wide bandwidth capability is tuned by an applied voltage or current. The oscillator obtains its feedback coupling by means of a differential amplifier which greatly reduces the second order temperature versus frequency drift. This is accomplished by forcing the oscillator to trip under conditions which greatly reduce V.sub.BE in the switching transistors.

Abstract: In an automatic tape assembly process an IC chip is bonded to the finger pattern created in a metal assembly tape. Then the housing is applied to encapsulate the IC during assembly. An insulating strip is then applied to the metal fingers that will ultimately become the packaged device loads. The strip is located just inside that point where the fingers will be excised from the tape so that after excision the strip will hold the leads in position for testing and handling.

Abstract: A current responsive sense amplifier circuit is used in a semiconductor memory. The circuit includes means for reducing the voltage swings that are associated with the binary logic states.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.

Abstract: A differential current sense amplifier is shown suitable for high speed semiconductor memory sensing. A reference current generation circuit is also developed for operating a plurality of sense amplifiers.

Abstract: A voltage reference is developed by operating a pair of different threshold CMOS transistors as a differential linear amplifier with the reference voltage value determined as an input offset voltage. The differential amplifier consists of an input stage with controlled offset, a high gain inverter and an output stage which is directly coupled back to the inverting input. The circuit is biased up using a depletion transistor at zero bias and a current mirror configuration for supplying all stages.

Abstract: A pair of CMOS inverters are cross coupled in a latching configuration. Both inverter supply terminals are coupled to complementary toggles that can render the inverters operative or inoperative. First, the inverters are rendered inoperative. An output switch is coupled between the output nodes so that the inverter's output nodes can be driven to the same potential, thus canceling any offset voltage. An input switch produces sampling over a time interval that extends beyond the output switch on period. After the sampling period, the toggles are operated to turn the inverters on and to produce a latch state determined by the potential change present in the sampling interval.

Abstract: A modulator circuit is disclosed in which a pair of differentially modulated direct currents are mirrored to an output. A control potential acts to vary the modulation without changing the direct current values. A CMOS version of a complete variable gain amplifier is detailed in which the common mode output is V.sub.CC /2 and is not changed with variations in the gain control potential or the input common mode potential.

Abstract: A carrier current receiver employs a comparator driven differentially to square a received data signal. The same drive signal is applied to a sample and hold circuit in which a capacitor is charged to a level that is related to the data signal offset. A voltage-to-current converter responds to the capacitor charge and feeds a current to the input where it acts to correct the offset.