Patents Represented by Attorney Mikio Ishimaru
  • Patent number: 8304834
    Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: November 6, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
  • Patent number: 8293546
    Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Soon Yoeng Tan, Huey Ming Chong, Byoung-Il Choi, Soo Muay Goh
  • Patent number: 8283193
    Abstract: A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: October 9, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Soon Yoeng Tan, Teck Jung Tang
  • Patent number: 8245388
    Abstract: A method of operation of a programmer actuator system includes: placing a programming assembly, having socket boxes, in the programming actuator system; and clamping the programming assembly in the programming actuator system using a pivoting arm bracket.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: August 21, 2012
    Assignee: Data I/O Corporation
    Inventor: Rossen Atanassov Rachkov
  • Patent number: 8174127
    Abstract: A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: May 8, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, Jr., Dioscoro A. Merilo
  • Patent number: 8163600
    Abstract: A bridge stack integrated circuit package-on-package system is provided including forming a first integrated circuit package system having a first substrate, forming a second integrated circuit package system having a second substrate, and mounting a bridge integrated circuit package system on the first substrate and on the second substrate.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 24, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Il Kwon Shim, Byung Joon Han
  • Patent number: 8158513
    Abstract: A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: April 17, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhihong Mai, Suey Li Toh, Pik Kee Tan, Jeffrey C. Lam, Liang-Choo Hsia
  • Patent number: 8153478
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 10, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Patent number: 8148208
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 3, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8148825
    Abstract: An integrated circuit package system includes: providing a lead terminal; forming a dummy lead near the lead terminal; positioning a base integrated circuit adjacent the lead terminal and the dummy lead; connecting a die connector to the base integrated circuit and the dummy lead; mounting a stackable integrated circuit over the base integrated circuit; and connecting another of the die connector to the stackable integrated circuit and the dummy lead.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 3, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Jeffrey D. Punzalan
  • Patent number: 8141247
    Abstract: A method of manufacture of an integrated circuit package-on-package system includes providing a base package and providing solder caps on the top of the base package configured to protrude above subsequent resin bleed, the resin bleed extending to an edge of the base package, and configured for merging with solder balls of a top package to form larger solder balls between such a top package and the base package.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8143098
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts along an interconnect perimeter region of the interposer, the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region; and mounting an integrated circuit over the device contacts.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Sharon Ooi, Reza Argenty Pagaila
  • Patent number: 8143711
    Abstract: An integrated circuit package system includes: a carrier; a device structure in an offset location over the carrier with the device structure having a bond pad and a contact pad; an electrical interconnect between the bond pad and the carrier; an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and a package encapsulation adjacent to the anti-flash structure and over the carrier.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua
  • Patent number: 8143107
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Il Kwon Shim, Seng Guan Chow
  • Patent number: 8143103
    Abstract: A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Young-Joon Kim, YoRim Lee
  • Patent number: 8143096
    Abstract: An integrated circuit package system includes: providing a substrate having a top side with a trace conductor connected to a bottom side with a system interconnect; forming a bump ring on the substrate, the bump ring having an inner cavity area over the trace conductor and an outer bump area; applying a substrate mask layer adjacent a perimeter of the outer bump area; connecting a device to the trace conductor below the bump ring; and applying a compound between the device and the substrate.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: March 27, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: SooMoon Park, KyungHoon Lee
  • Patent number: 8143104
    Abstract: A method for manufacturing a ball grid array package stacking system includes: providing a base substrate; coupling an integrated circuit to the base substrate; coupling a stacking substrate over the base substrate; mounting a heat spreader, having an access port, around the base substrate and the stacking substrate; and coupling a stacked integrated circuit to the stacking substrate through the access port.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: Jong-Woo Ha
  • Patent number: 8143102
    Abstract: An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the shaped cross-section of the relief region.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 27, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Sang-Ho Lee, Jong Wook Ju
  • Patent number: 8138051
    Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: March 20, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yemin Dong, Purakh Raj Verma, Xin Zou, Chao Cheng, Shao-fu Sanford Chu
  • Patent number: 8138595
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an elevated contact above and between a lead and a die pad that is coplanar with the lead; connecting an integrated circuit and the lead; attaching a jumper interconnect between the elevated contact and the lead; and forming an encapsulant over the integrated circuit, the lead, the die pad, the elevated contact, and the jumper interconnect, the encapsulant having a recess in a base side with the elevated contact exposed in the recess and the lead exposed from the base side.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: March 20, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan