Patents Represented by Attorney Mikio Ishimaru

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  • System for solder ball inner stacking module connection
    Patent number: 8067828
    Abstract: An integrated circuit package-in-package system including: providing a substrate; mounting a structure over the substrate; supporting an inner stacking module cantilevered over the substrate by an electrical interconnect connected to the substrate, the electrical interconnect forming a gap between the inner stacking module and the structure controlled by the size of the electrical interconnect; and encapsulating the structure and inner stacking module with an encapsulation.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Chan Hoon Ko, Soo-San Park
  • Stacked integrated circuit package system and method for manufacturing thereof
    Patent number: 8067268
    Abstract: A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Flynn Carson, Jong-Woo Ha, BumJoon Hong, SeongMin Lee
  • Integrated circuit package system with encapsulation lock
    Patent number: 8067271
    Abstract: An integrated circuit package system is provided including forming an external interconnect and a tie bar, forming a lead tip and a lead body of the external interconnect, forming a hole in the external interconnect, forming a slot in the tie bar, connecting an integrated circuit die and the external interconnect, and molding the external interconnect and the tie bar with the slot and the hole filled.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Sung Uk Yang
  • Integrated circuit package system for package stacking and manufacturing method thereof
    Patent number: 8067272
    Abstract: A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second integrated circuit die and the base, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Young Cheol Kim, Koo Hong Lee, Jae Hak Yee, Ii Kwon Shim
  • Integrated circuit package system for stackable devices
    Patent number: 8067307
    Abstract: An integrated circuit package system comprising: providing a package die; and connecting a connector lead having a first connector end with a protruded connection surface and a lowered structure over the package die.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, Sang-Ho Lee, Soo-San Park
  • Embedded integrated circuit package system and method of manufacture thereof
    Patent number: 8067832
    Abstract: A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Dioscoro A. Merilo, Seng Guan Chow
  • Integrated circuit packaging system having asymmetric encapsulation structures and method of manufacture thereof
    Patent number: 8063477
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first internal integrated circuit structure and a second internal integrated circuit structure over the substrate; connecting the first internal integrated circuit structure and the second internal integrated circuit structure to the substrate with internal interconnects; forming asymmetric encapsulation structures above the first internal integrated circuit structure and the second internal integrated circuit structure; and encapsulating the first internal integrated circuit structure and the internal interconnects with an encapsulation.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: November 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Semiconductor package system with through silicon via interposer
    Patent number: 8063475
    Abstract: A semiconductor package system includes: providing a top package, a through silicon via interposer embedded in the top package; providing a bottom package having a bottom semiconductor die with a top connection adjacent the center active face thereof, a substrate interposer being embedded in the bottom package, the bottom semiconductor die being attached to the substrate interposer; and attaching the top package to the bottom package, the top package having the through silicon via interposer having a via connected to the top connection.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: November 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, DeokKyung Yang, Seung Won Kim
  • Integrated circuit package system with ground bonds
    Patent number: 8062934
    Abstract: An integrated circuit package system comprising: forming leads adjacent a die paddle having a die pad extension; forming a region having one of the leads depopulated for the die pad extension; and connecting an integrated circuit die to the die pad extension.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Method of manufacture of an integrated circuit system with self-aligned isolation structures
    Patent number: 8053327
    Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: November 8, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
  • Integrated circuit package system with flexible substrate and recessed package
    Patent number: 8050047
    Abstract: An integrated circuit package system includes: providing a flexible circuit substrate having a fold; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a recessed encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: November 1, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Il Kwon Shim, Byung Joon Han, Kambhampati Ramakrishna
  • Integrated circuit package system with insulator over circuitry
    Patent number: 8049314
    Abstract: An integrated circuit package system includes: providing a connection array; attaching a base integrated circuit adjacent the connection array; attaching a package integrated circuit over the base integrated circuit; attaching a package die connector to the package integrated circuit and the connection array; and applying a wire-in-film insulator over the package integrated circuit, the package die connector, the base integrated circuit, and the connection array, wherein the connection array is partially exposed.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Method and apparatus for removing radiation side lobes
    Patent number: 8048588
    Abstract: A method and structure for removing side lobes is provided by positioning first and second radiation transparent regions of respective first and second phases at a first plane with the first and second phases being substantially out of phase. Further, positioning the first and the second region to cause radiation at a second plane to be neutralized in a first region, not to be neutralized in a second region, and to have a side lobe in a third region. Further, positioning a non-transparent region at the first plane to assure radiation at the second plane to be neutralized in the first region and positioning a third radiation transparent region of the first or second phase at the first plane to neutralize the side lobes in the third region at the second plane.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sia Kim Tan, Soon Yoeng Tan, Qunying Lin, Huey Ming Chong, Liang-Choo Hsia
  • Integrated circuit package-in-package system and method for making thereof
    Patent number: 8049322
    Abstract: A method for making an integrated circuit package-in-package system includes: forming a first integrated circuit package including a first device and a first substrate and having a first interface; stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package; and fitting the first interface directly on the second interface.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: November 1, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Choong Bin Yim, Hyeog Chan Kwon, Jong-Woo Ha
  • Integrated circuit package system with redistribution layer
    Patent number: 8043894
    Abstract: An integrated circuit package system includes forming a first external interconnect having both a first side and a second side that is an opposing side to the first side; forming a first encapsulation around a first integrated circuit and the first external interconnect with the first side, the second side, and the first active side of the first integrated circuit exposed; forming a planar interconnect between the first active side and the second side; forming a second encapsulation covering the planar interconnect and the first active side; connecting a second integrated circuit over the first integrated circuit and the first side; and forming a top encapsulation over the second integrated circuit.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: October 25, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Henry Descalzo Bathan
  • Ball grid array package stacking system
    Patent number: 8039942
    Abstract: A ball grid array package stacking system includes: providing a base substrate; coupling an integrated circuit to the base substrate; coupling a stacking substrate over the base substrate; mounting a heat spreader, having an access port, around the base substrate and the stacking substrate; and coupling a stacked integrated circuit to the stacking substrate through the access port.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Jong-Woo Ha
  • Leadless semiconductor chip carrier system
    Patent number: 8039311
    Abstract: A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: October 18, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Heap Hoe Kuan, Rui Huang, Seng Guan Chow
  • Integrated circuit package system with different mold locking features
    Patent number: 8039947
    Abstract: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead and the first outer lead, and encapsulating the integrated circuit die and the first side lock.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Integrated circuit package system including wafer level spacer
    Patent number: 8039365
    Abstract: An integrated circuit package system that includes providing a wafer level spacer including apertures, which define unit spacers that are interconnected, and configuring the unit spacers to substantially align over devices formed within a substrate.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Sang-Ho Lee, Jong-Woo Ha, Soo-San Park
  • Memory storage device
    Patent number: D648729
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: November 15, 2011
    Assignees: Clevx, LLC, Corsair Memory, Inc.
    Inventors: John Beekley, Lev M. Bolotin, Gary Bordenkircher, James Carlton, Kevin M. Conley, Robert Hubler, Simon B. Johnson, Andrew J. Paul