Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base conductive material on opposite sides of the base substrate; connecting an internal interconnect having a substantially spherical shape on the base substrate; forming a top substrate having a top conductive material on opposite sides of the top substrate with an upper component thereon facing the base substrate; and attaching the top substrate on the internal interconnect.
Type:
Grant
Filed:
June 20, 2009
Date of Patent:
January 31, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
Abstract: A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.
Type:
Grant
Filed:
January 13, 2011
Date of Patent:
January 24, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Tae Sung Jeong, Hyeog Chan Kwon, Youngcheol Kim
Abstract: An integrated package system with die and package combination includes forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit.
Type:
Grant
Filed:
August 20, 2009
Date of Patent:
January 24, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
Seng Guan Chow, Ming Ying, Il Kwon Shim
Abstract: An integrated circuit package system includes: connecting a carrier and an integrated circuit mounted thereover; mounting an interposer, having an opening, over the integrated circuit; connecting an interconnect between the interposer and the carrier through the opening; and forming an encapsulation planar with a carrier vertical side of the carrier and an interposer vertical side of the interposer.
Type:
Grant
Filed:
August 19, 2008
Date of Patent:
January 24, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
HyungSang Park, In Sang Yoon, DeokKyung Yang, Soo-San Park
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
Type:
Grant
Filed:
November 19, 2010
Date of Patent:
January 10, 2012
Assignee:
Stats Chippac Ltd.
Inventors:
A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
Abstract: A method for manufacturing of an integrated circuit package-in-package system includes: mounting a first integrated circuit device over a substrate; mounting an integrated circuit package system having an inner encapsulation over the first integrated circuit device with a first offset; mounting a second integrated circuit device over the first integrated circuit device and adjacent to the integrated circuit package system; connecting the integrated circuit package system and the substrate; and forming a package encapsulation as a cover for the first integrated circuit device, the integrated circuit package system, and the second integrated circuit device.
Type:
Grant
Filed:
August 30, 2010
Date of Patent:
January 10, 2012
Assignee:
STATS Chippac Ltd.
Inventors:
Soo-San Park, BumJoon Hong, Sang-Ho Lee, Jong-Woo Ha
Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead tip and a lead body, forming a recess in the lead body from a lead body top surface, connecting an integrated circuit die and the external interconnect, and molding the external interconnect with the recess filled.
Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.
Abstract: A video coding system is provided including generating a motion vector for a macro block in a picture, the motion vectors indicative of displacement of an object in the macro block; grouping a cluster of the motion vectors; and adjusting a dynamic quantization parameter modulation of a subsequent picture based on the grouping for displaying the displacement of the object in the subsequent picture.
Type:
Grant
Filed:
January 5, 2007
Date of Patent:
January 3, 2012
Assignees:
Sony Corporation, Sony Electronics Inc.
Abstract: An integrated circuit package system is provided in which an interposer of predetermined thickness including a central cavity is formed. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and second packages.
Abstract: An integrated circuit package system includes a bottom pad with a bottom tie bar, attaching an integrated circuit die over the bottom pad, attaching a top pad with a top tie bar, over the integrated circuit die, and applying an encapsulant wherein the top tie bar integral to the top pad, is exposed on a side of the encapsulant.
Abstract: An integrated circuit package system includes: providing an interposer having a bond pad and a contact pad; mounting the interposer in an offset location over a carrier with an exposed side of the interposer coplanar with an edge of the carrier; connecting an electrical interconnect between bond pad and the carrier; and forming a package encapsulation over the carrier and the electrical interconnect with both the contact pad and the exposed side of the interposer not covered.
Type:
Grant
Filed:
December 12, 2007
Date of Patent:
December 27, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Seng Guan Chow, Linda Pei Ee Chua, Heap Hoe Kuan
Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.
Type:
Grant
Filed:
October 29, 2009
Date of Patent:
December 20, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; and forming an encapsulation that encapsulates the integrated circuit, the routing structure.
Type:
Grant
Filed:
May 27, 2009
Date of Patent:
December 20, 2011
Assignee:
STATS ChipPAC Ltd.
Inventors:
A Leam Choi, Kenny Lee, In Sang Yoon, HanGil Shin
Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.
Type:
Grant
Filed:
November 19, 2008
Date of Patent:
December 20, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Seng Guan Chow, Heap Hoe Kuan, Rui Huang
Abstract: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.
Abstract: An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die.
Type:
Grant
Filed:
December 17, 2007
Date of Patent:
November 29, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
WonJun Ko, Jong Wook Ju, SeungYong Chai, Taeg Ki Lim, Ja Eun Yun
Abstract: An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle.
Type:
Grant
Filed:
September 28, 2007
Date of Patent:
November 29, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Abelardo Jr. Hadap Advincula, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
Type:
Grant
Filed:
September 16, 2005
Date of Patent:
November 29, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju