Abstract: A grease filter has a filtering portion configured such that fumes enter a major face thereof and flow through a grease extraction filter therewithin in a direction parallel to the major face. A frame that fits into an opening of a hood defines a box structure that is configured to allow flow from the end (or ends) of the filtering portion where flow exits. The frame permits the flow to exit to a side opposite the face even when the frame is surrounded, edgewise, by a solid structure of the hood opening.

Abstract: A contactless electronic device comprises a semiconductor integrated circuit device, a plurality of antennas (or antenna coils) for receiving high-frequency signals supplied by radio waves or electromagnetic waves having different frequencies. An interface judgment circuit judges which antenna the high-frequency signals are inputted through, and according to a result of the judgment, the operation of the semiconductor integrated circuit device is changed. In this manner, the contactless electronic device becomes possible to respond to a plurality of communication protocols using high-frequency signals having different frequencies, while contactless electronic devices have been impossible to respond to communication protocols using various high-frequency signals.

Abstract: The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film.

Abstract: The present invention aims to efficiently calibrate the characteristics of a pair of reception or transmission low-pass filters by a receiving or transmitting circuit. A semiconductor integrated circuit includes an RF receiver that processes an RF reception signal, an RF transmitter that generates an RF transmission signal and a frequency synthesizer. A reception low-pass filter of the RF receiver suppresses undesired components contained in I and Q baseband reception signals. A transmission low-pass filter of the RF transmitter suppresses noise due to D/A conversion, which is contained in I and Q transmission analog baseband signals. A calibration test signal is supplied to the inputs of the pair of reception or transmission low-pass filters. A difference in phase between the pair of filters is detected by a phase detection unit. A calibration controller calibrates a relative mismatch between the cut-off frequencies of the pair of filters.

Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.

Abstract: To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the principal plane across the charge storage film, and wherein a memory channel region located beneath the charge storage film of the principal plane of the silicon substrate contains fluorine.

Abstract: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.

Abstract: When generating an RF test signal for mismatch calibration for receiver in order to calibrate reception mismatch of an I-phase signal and a Q-phase signal that are output from demodulated signal processing circuits coupled to mixers for receiving, a Tx VCO avoids covering the higher frequency of an RF received signal in an FDD system. An RF test signal generating unit generates, in a calibration mode of a mismatch calibration for receiver circuit, the RF test signal by using an oscillation output signal of the Tx VCO and other circuits, and supplies the same to the mixers for receiving via a switch. The RF test signal has a frequency within an RF reception frequency band that is higher than that of an RF transmission signal with the maximum frequency band of multiband radio frequency communications. By switching the switch in a reception mode, an output of a low-noise amplifier that amplifies the RF received signal received by an antenna is supplied to each of the mixers for receiving.

Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Abstract: A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.

Abstract: In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.

Abstract: Boundary acoustic wave devices are both compact and possess excellent temperature stability. Yet these devices have the drawback that the Q value cannot be raised, and a high cost thin-film technology is required. This invention provides a boundary acoustic wave device possessing excellent Q value along with a low cost. A boundary acoustic wave device including a film whose main ingredient is aluminum at a thickness hm, and a shorting reflector (thickness hr) and a IDT with an electrode finger period of lambda, are patterned onto the surface of a theta YX-LN single crystalline piezoelectric substrate; and a silicon oxide film with a thickness h1 and an aluminum nitride film 6 with a thickness h2 are formed on that comb electrode and reflector, wherein: 2.5?hr/??8.5% is obtained.

Abstract: A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.

Abstract: A sample inspection apparatus in which a fault in a semiconductor sample can be measured and analyzed efficiently. A plurality of probes are brought into contact with the sample. The sample is irradiated with an electron beam while a current flowing through the probes is measured. Signals from at least two probes are supplied to an image processing unit so as to form an absorbed electron current image. A difference between images obtained in accordance with a temperature change of the sample is obtained. A faulty point is identified from the difference between the images.

Abstract: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.