Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

Abstract: A fluorescence detecting apparatus includes a light detecting device disposed in a light path of fluorescence generated in an illuminated area of a specimen and a barrier filter disposed in the light path toward the light detecting device to exhibit transparency for each of a plurality of fluorescences having separated wavelength bands.

Abstract: An apparatus for handling articles (4) through a multi-stage process, the apparatus comprising at least one rotatable process turret (2) having a number of pockets (3), wherein each pocket (3) is adapted to support an article (4). The pockets (3) are arranged in groups and each group of pockets (3A, 3B, 3C) has associated tooling (5A, 5B, 5C), which carries out one stage of the process. The articles (4) are initially fed into one group of pockets (3A) only. A re-phase means (6) is provided to transfer the article (4) from one group of pockets (3A, 3B) to another (3B, 3C).

Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

Abstract: Provided is a control technique of a PWM conversion type power converter capable of compensating for a voltage error due to voltage drop mainly at a switching element and managing a switching time of a PWM signal at the same time, and capable of suppressing increase/decrease of software operation load and addition of a hardware circuit to the minimum. A semiconductor integrated circuit having a PWM signal generating unit which generates a PWM signal is provided with a PWM timer unit including a counter counting a pulse width of a pulse signal inputted from the outside with delay from a PWM signal, a register loading a counter value of the counter in synchronization with the PWM signal, and an A/D converting unit converting an analog signal serving as a source signal of the pulse signal inputted from the outside to a digital signal.

Abstract: A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.

Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.

Abstract: A method of automatically identifying relevant or suspect data during a digital forensic investigation is described. Software accepts as input raw data which are extracted from various digital data sources. The software or digital forensic and data identification application determines to which one or more identification modules the unknown raw data should be delivered to for processing. This determination is based on the type of data in the extracted raw data coming into the application. Suspect or relevant data that are identified includes that data that are identical to or similar to the extracted unknown raw data. If there are suspect data, the application transmits a message or alert to interested parties or stores the findings/report on an a storage device. In this manner, the suspect data are identified automatically, without intervention by a human being.

Abstract: An imaging lens includes a first lens group having a positive refractive power, an aperture stop, and a second lens group having a positive refractive power, which are disposed in order from an object. The first lens group has a first lens component having a negative refractive power and a second lens component having a positive refractive power, which are disposed in order from the object, and conditions expressed by the expressions 0.12<f/f1<0.47 and 0.016<D12/f<0.079 are satisfied, when f1 is a focal length of the first lens group, f is a focal length of the imaging lens, and D12 is an air distance between the first lens component and the second lens component of the first lens group.

Abstract: A projection device includes: a projector unit that has at least a light source and a projection optical system housed in a chassis; a control unit that is assembled with a chassis separate from the chassis of the projector unit; and a rotation support member that rotatably supports the projector unit and the control unit around a rotation axis that extends perpendicular to a surface of the chassis of the projector unit and a surface of the chassis of the control unit, with these surfaces facing to one another.

Abstract: A zoom lens is provided with comprising a plurality of lens groups including, in order from an object side, a first lens group G1 having positive refractive power, a second lens group G2 having negative refractive power, a third lens group G3, and a fourth lens group G4, the third lens group G3 including, in order from the object side, a first positive lens of the third lens group, a negative lens of the third lens group, and a second positive lens of the third lens group, and a given conditional expression being satisfied, thereby excellently correcting chromatic aberration in a farther away shooting range, capable of having excellent optical performance with being compact.

Abstract: A communication system for use with a packet-based network is disclosed. A first node is configured to transmit circuit data in data packets across the network. A second node is configured to receive the data packets from the network and serialize the synchronous data. The second node comprises a configurable buffer, the buffer being configurable to adjust to network packet delay variance through analysis of packet delay variance as measured over at least one period of time.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.

Abstract: A steelmaking process is disclosed. The process includes producing molten steel and molten steelmaking slag in a steelmaking process, the steelmaking slag including iron units and flux units, and thereafter producing molten iron in a molten bath based direct smelting process using a substantial portion of the steelmaking slag as part of the feed material requirements for the direct smelting process. A direct smelting process is also disclosed. The process includes pre-treating ferrous material including steelmaking slag and thereafter direct smelting molten iron using the pretreated ferrous material as part of the feed material for the process.

Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.