Patents Represented by Attorney Miles & Stockbridge P.C.
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Patent number: 7976711Abstract: A method and device for blood treatments that use fluids such as dialysate and replacement fluid for renal replacement therapy. In an embodiment, fluid is passed either by pump or passively by gravity feed, through a microporous sterilization filter from a fluid source to a replacement fluid container. The latter forms a batch that may be used during treatment. The advantage of forming the batch before treatment is that the rate of filtering needn't match the rate of consumption during treatment. As a result, the sterilization filter can have a small capacity. In another embodiment, a filter is placed immediately prior to the point at which the sterile fluid is consumed by the treatment process. The latter may be used in combination with the former embodiment as a last-chance guarantee of sterility and/or that the fluid is free of air bubbles. It may also be used as the primary means of sterile-filtration.Type: GrantFiled: May 24, 2010Date of Patent: July 12, 2011Assignee: NxStage Medical, Inc.Inventors: James M. Brugger, Jeffrey H. Burbank, Brian C. Green
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Patent number: 7971791Abstract: A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes.Type: GrantFiled: July 3, 2003Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Patent number: 7974012Abstract: A zoom lens system has a front lens group and a rear lens group along the optical axis and in order from the object side. The rear lens group has a first lens unit having a positive refracting power, a second lens unit having a negative refracting power, and a third lens unit having a positive refracting power. Upon zooming from a wide-angle end state to a telephoto end state, a space between the front lens group and the first lens unit varies, a space between the first lens unit and the second lens unit increases, and a space between the second lens unit and the third lens unit decreases. At least a part of the second lens unit is movable so as to have a component in a direction perpendicular to the optical axis.Type: GrantFiled: March 20, 2009Date of Patent: July 5, 2011Assignee: Nikon CorporationInventor: Satoshi Yamaguchi
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Patent number: 7972886Abstract: Provided is a MEMS device which is robust to the misalignment and does not require the double-side wafer processing in the manufacture of a MEMS device such as an angular velocity sensor, an acceleration sensor, a combined sensor or a micromirror. After preparing a substrate having a space therein, holes are formed in a device layer at positions where fixed components such as a fixing portion, a terminal portion and a base that are fixed to a supporting substrate are to be formed, and the holes are filled with a fixing material so that the fixing material reaches the supporting substrate, thereby fixing the device layer around the holes to the supporting substrate.Type: GrantFiled: June 20, 2008Date of Patent: July 5, 2011Assignee: Hitachi, Ltd.Inventors: Heewon Jeong, Yasushi Goto, Yuko Hanaoka, Tsukasa Fujimori
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Patent number: 7971793Abstract: The present invention provides a memory card equipped with an interface controller connected to external connecting terminals, a memory connected to the interface controller, and a security controller connected to the interface controller. A second external connecting terminal capable of supplying an operating power supply to the security controller is provided aside from a first external connecting terminal which supplies an operating power supply to the interface controller and the memory. An interface unit of the interface controller connected to the security controller receives the operating power supply from the second external connecting terminal and thereby enables a stop of the supply of the operating power supply from the first external connecting terminal. Even if the supply of the operating power supply to the interface controller is cut off, the output of the interface unit is not brought to an indefinite state.Type: GrantFiled: November 27, 2007Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Tamaki Wada, Michiaki Sugiyama, Junichiro Osako
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Patent number: 7973573Abstract: A semiconductor integrated circuit having a plurality of ultrasound pulsers corresponding to a plurality of respective channels, and integrally formed on a small area. The ultrasound pulsers each include a MOSFET gate drive circuit in which an input voltage pulse is converted into a current pulse, and the current pulse is converted again into a voltage pulse on the basis of a high potential side voltage +HV, and a low potential side voltage ?HV, applied to a transducer drive circuit, and in which a voltage level shift in the input voltage pulse is attained, and a voltage pulse swing is generated by the MOSFET gate drive circuit on the basis of the high potential side voltage +HV, and the low potential side voltage ?HV. The MOSFET gate drive circuit is DC-coupled with the transducer drive circuit.Type: GrantFiled: February 4, 2010Date of Patent: July 5, 2011Assignee: Hitachi, Ltd.Inventors: Satoshi Hanazawa, Hiroyasu Yoshizawa
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Patent number: 7968939Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: November 28, 2010Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Patent number: 7968368Abstract: A method of manufacturing a field effect transistor, which has high alignment accuracy between a gate electrode and source and drain electrodes and can provide a transparent device at a low cost. Since a patterned light blocking film is formed on the rear side of a substrate and used as a photomask for forming a gate electrode pattern and a source and drain electrode pattern on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, a method of manufacturing a high-accuracy low-cost field effect transistor can be provided.Type: GrantFiled: January 28, 2010Date of Patent: June 28, 2011Assignee: Hitachi, Ltd.Inventors: Hironori Wakana, Hiroyuki Uchiyama, Tetsufumi Kawamura, Shinichi Saito
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Patent number: 7967123Abstract: The present invention provides a wet-type multi-plate friction engaging apparatus comprising a clutch portion including internally toothed plates and a piston adapted to apply an urging force for engaging the internally toothed plates and wherein load acting portions acting on the clutch portion are arranged on both sides of the clutch portion, and a contact area of the load acting portion through which the load acting portion is contacted with the clutch portion is located in a predetermined range between about 20% of a radial width of a friction engaging portion from a central position of the friction engaging portion in an outer diameter direction and about 20% of the radial width of the friction engaging portion in an inner diameter direction, and a radial width of the contact area is smaller than about 10% of the radial width of the friction engaging portion.Type: GrantFiled: February 27, 2008Date of Patent: June 28, 2011Assignee: NSK-Warner K.KInventors: Yosuke Ikeda, Tomoyuki Miyazaki
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Patent number: 7968924Abstract: In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process.Type: GrantFiled: September 29, 2008Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventor: Akihiko Sato
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Patent number: 7969760Abstract: The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.Type: GrantFiled: April 26, 2007Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Tomoyuki Ishii, Yoshitaka Sasago, Hideaki Kurata, Toshiyuki Mine
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Patent number: 7968966Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.Type: GrantFiled: September 21, 2009Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
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Patent number: 7964500Abstract: To solve a problem that it becomes difficult to lower contact resistance between nickel-based metal silicide and metal for contact as the result of the miniaturization of the hole. One invention of the present application is a method of manufacturing a semiconductor integrated circuit device having a MISFET subjected to silicidation of a source/drain region and the like by nickel-based metal silicide, the method performing a heat treatment for the upper surface of a silicide film in a non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components, before forming a barrier metal at a contact hole provided at a pre-metal insulating film.Type: GrantFiled: February 27, 2010Date of Patent: June 21, 2011Assignee: Renesas Electronics CorporationInventor: Takuya Futase
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Patent number: 7966512Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: January 4, 2009Date of Patent: June 21, 2011Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
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Patent number: 7966594Abstract: The invention relates to an automated method for inserting dummy surfaces (95) into the various layers of the physical design (121) of multilayer integrated circuits organized in interconnected units (2) containing interconnected blocks (30) composed of interconnected cells (3), implemented by an integrated circuit design system (100). The multilayer integrated circuit design (121), stored in the design system (100) is implemented layer by layer, through selective insertion of patterns of dummy surfaces (95), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design (121) of the integrated circuits, by means of individual implementation of the interconnected blocks (30) and first interconnection routing (31) for said interconnected blocks (30) and individual implementation of the interconnected units (2) and second interconnection routing (22) for said interconnected units (2).Type: GrantFiled: January 14, 2008Date of Patent: June 21, 2011Assignee: Bull S.A.Inventors: Marta Zorrilla, Vivian Blanchard
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Patent number: 7964509Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).Type: GrantFiled: January 22, 2008Date of Patent: June 21, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi
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Patent number: 7961387Abstract: An observation device has an ocular lens and an objective lens and is adapted to observe through the ocular lens an intermediate image of an object formed by the objective lens. The observation device further includes a display section provided either on a light path connecting the ocular lens and the objective lens or on a light path branched off from the light path and displaying an image, and a light path switching section provided on the light path connecting the ocular lens and the objective lens and switching the light to be guided from the ocular lens to the objective lens and the image displayed on the display section to be guided to the ocular lens or the objective lens, thereby providing a small-sized observation device and binoculars having a display function.Type: GrantFiled: March 1, 2005Date of Patent: June 14, 2011Assignees: Nikon Vision Co. Ltd., Nikon CorporationInventors: Shunichi Haga, Kenji Yamada
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Patent number: 7961545Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.Type: GrantFiled: December 3, 2009Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
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Patent number: 7960696Abstract: As an aspect for realizing accurate observation, inspection, or measurement of the contact hole with large aspect ratio, a method and a device to scan a second electron beam after scanning a first electron beam to a sample to charge the sample are proposed wherein the beam diameter of the first electron beam is made larger than the beam diameter of the second electron beam.Type: GrantFiled: September 25, 2008Date of Patent: June 14, 2011Assignee: Hitachi High-Technologies CorporationInventors: Makoto Ezumi, Satoru Iwama, Junichi Kakuta, Takahiro Sato, Akira Ikegami
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Patent number: 7962035Abstract: Providing a viewfinder optical system capable of obtaining given magnification and a given eyepoint, suitable for an SLR digital camera and an SLR camera, an optical apparatus equipped therewith, and a method for expanding observation. The viewfinder optical system M including an eyepiece optical system 15 for observing a real image of an object formed by an objective lens 11 through an erecting image forming member 14, the eyepiece optical system 15 consisting of, in order from the object along an optical axis, a double concave negative lens, a double convex positive lens, a lens, and a meniscus lens having a convex surface facing the object; an optical apparatus 10 equipped therewith; and a method for expanding observation.Type: GrantFiled: June 26, 2007Date of Patent: June 14, 2011Assignee: Nikon CorporationInventor: Daisaku Arai