Abstract: A fastener, for use with a sheet-shaped member, comprises a tubular shank, a plurality of holding pieces extending outward from a first end of the shank, a flange extending outward from a second end of the shank, and a plurality of stud-engagement pawls extending into the interior of the shank. The shank has a length less than that of a stem of a stud fixed to a mounting member with which the fastener is to be engaged. When the stud is fully inserted into the tubular shank, the sheet-shaped member is fastened to the stud and the stud stem protrudes from a surface of the sheet-shaped member. The protruding portion of the stem allows an auxiliary member to be mounted thereto.
Abstract: A continuously variable ratio transmission including a planetary gear set having a sun gear, a ring gear, and a planet carrier having at least two planet gears carried thereon, a control element including a servogenerator capable of generating electric power, and at least one auxillary field coil adapted to be operatively connected to an output means to influence a power output level and AC power frequency of the output means, the at least one auxillary field coil being powered by the servogenerator and constituting a load to the servogenerator, the speed of the servogenerator being capable of being controlled by the load; and a means for controlling an electrical current to the at least one auxiliary field coil form the servogenerator; where the servogenerator is capable of being driven to produce electrical power by a rotation of one of the sun gear, the ring gear, and the planet carrier.
Abstract: A capacitor uses niobium pentoxide in the manufacture of a semiconductor device. The niobium pentoxide has a low crystallization temperature of 600° C. that provides control over the oxidation of the bottom electrode during heat-treatment. A dielectric constituent present as an amorphous oxide along the grain boundaries of polycrystalline niobium pentoxide is used for a capacitor insulator, thereby providing a method to decrease the leakage current along the grain boundary of niobium pentoxide and to realize a high dielectric constant and low-temperature crystallization.
Abstract: A method for designing a logic circuit and a CAD program which allow a logic circuit with desired performance to be designed in a short period of time by suppressing the elongation of a logic design period for achieving a circuit area, an operating speed, power consumption, and the like as target specifications are provided at low cost. Shorter-period and lower-cost design is accomplished by allowing a user to use a high-performance logic synthesis CAD program at no charge if he only checks circuit characteristics resulting from synthesis and collecting a fee if the user is satisfied with the resulting circuit characteristics and intends to use a gate level logic circuit. In a design phase which receives a register transfer level or operation level logic circuit and synthesizes a gate level logic circuit, desired circuit characteristics are obtainable in a short period of time at low cost.
Abstract: An exposure apparatus and method in which a mark on an object is illuminated, and plural pairs of two diffractive beams of same order are generated and directed to different reference gratings to detect positional information of the mark. Beams received from the different reference gratings have different order.
Abstract: There is provided a switching power supply device of hysteresis current mode control system which assures excellent response characteristic for change of output current and reduction of power consumption. In a switching regulator of hysteresis current mode control system, a sense resistor connected in series to a coil is eliminated, a serially connected resistor and a capacitor are connected in parallel to a coil in place of such sense resistor. Thereby, a potential of a connection node of these resistor and capacitor is inputted to a comparator circuit having the hysteresis characteristic for comparison with the reference voltage. Accordingly, a switch may be controlled for ON and OFF states.
Abstract: Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.
Abstract: Embodiments of the present invention relate to methods and systems suitable for de-convoluting a convoluted spectrum, such as by way of example, data obtained from a mass spectrometer.
Type:
Grant
Filed:
August 12, 2004
Date of Patent:
September 12, 2006
Assignee:
Applera Corporation
Inventors:
Darryl J. C. Pappin, Nikita Khainovski, Darryl D. Spencer
Abstract: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
Type:
Grant
Filed:
June 15, 2005
Date of Patent:
September 5, 2006
Assignees:
Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
Abstract: The object of the present invention is to provide an eyepiece lens having a large pupil diameter of 10 mm or more, securing higher magnification, equipped with a high quality diopter adjustment function at low cost. The eyepiece lens includes, in order from an eye point side EP, a negative meniscus lens L1 having a concave surface facing to the eye point side EP, a double convex lens L2, and a negative lens L3. Diopter of the eyepiece lens is adjusted by moving the double convex lens L2 along an optical axis. At least one surface of the double convex lens L2 has an aspherical surface having positive refractive power getting weaker in accordance with increase in a distance to the surface from the optical axis, and given conditional expressions are satisfied.
Abstract: The invention relates to a search engine (2) implemented by a decision application server (1) acting on a relational database (6) that contains a set of target records. The engine (2) is activated by queries for selecting records based on given criteria and comprises means (8) for preconditioning the database (6) supplying a preconditioned encoded table (10), periodically updated at the same time as the relational database (6) itself, to a machine with vectorial capabilities (9) in order for it to be processed. It also comprises means (7) for extracting target records, activated by the queries based on the result of the processing of the table (10) installed in the machine with vectorial capabilities (9), from the relational database (6). It particularly applies to data warehousing systems.
Abstract: The production of semiconductor devices manufactured through a plurality of manufacturing sites is unitarily managed and an appropriate production plan is instructed. A computer projects a production plan of an entire company based on various information. The production plan is provided to each manufacturing site as a production instruction and provided to each business person or customer as a storing reply or an order accepting period reply. If the projected production plan (possible production volume) does not coincide with a production plan (necessary production volume), parameters obtained by correcting production allocation, production capability, lead time, yield and the like are re-input from a parameter input terminal. Based on the corrected parameters, the computer re-projects the production plan and projects an optimum production plan.
Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.
Type:
Grant
Filed:
September 14, 2005
Date of Patent:
August 22, 2006
Assignees:
Renesas Technology Corp., Hitachi ULSI Systems Co., Inc.
Abstract: Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.
Abstract: Polyamines having the formula: or a salt thereof with a pharmaceutically acceptable acid wherein: R1-R6 may be the same or different and are alkyl, aryl, aryl alkyl, cycloalkyl, optionally having an alkyl chain interrupted by at least one etheric oxygen atom, or hydrogen; N1, N2, N3 and N4 are nitrogen atoms capable of protonation at physiological pH's; a and b may be the same or different and are integers from 1 to 4; A, B and C may be the same or different and are bridging groups which effectively maintain the distance between the nitrogen atoms such that the polyamines: (i) are capable of uptake by a target cell upon administration thereof to a human or non-human animal; and (ii) upon uptake by the target cell, competitively bind via an electrostatic interaction between the positively charged nitrogen atoms to substantially the same biological counter-anions as the intracellular natural polyamines in the target cell; the polyamines, upon binding to the biological counter-anion in the cell, functio
Type:
Grant
Filed:
September 4, 2002
Date of Patent:
August 22, 2006
Assignee:
University of Florida Research Foundation, Inc.
Abstract: In order to test whether a given signal of a complex circuit has the correct behavior, a method is provided which makes it possible to obtain in a computer memory a profile of states of other signals. In order to minimize the processing time and the memory space required to obtain this profile, the method uses two binary decision diagrams starting with a binary variable of said one signal, each with two binary decision subdiagrams. The method combines the binary decision subdiagrams so that the given signal is in a first state when the binary variable is at a first value and is not in this first logical state when the binary variable is at a second value.
Type:
Grant
Filed:
June 7, 2001
Date of Patent:
August 22, 2006
Assignee:
Bull, S.A.
Inventors:
Florence Akli, Alain Debreil, Christian Niquet
Abstract: There is provided a semiconductor integrated circuit that hardly causes an unnecessary operation time for variable control over an operating frequency and an internal power supply voltage. A CPU specifies an operational clock signal frequency to a clock generation circuit and an internal power supply voltage to a power supply circuit. The power supply circuit comprises a voltage regulator and a determination circuit to determine a transition state to a specified internal power supply voltage. The CPU uses a first signal to notify which time point the power supply voltage variable control start to the power supply circuit. The power supply circuit returns a second signal to the CPU to notify at which time point the power supply voltage variable control terminated.
Abstract: A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.
Abstract: There is provided a switching power supply device of hysteresis current mode control system which assures excellent response characteristic for change of output current and reduction of power consumption. In a switching regulator of hysteresis current mode control system, a sense resistor connected in series to a coil is eliminated, a serially connected resistor and a capacitor are connected in parallel to a coil in place of such sense resistor. Thereby, a potential of a connection node of these resistor and capacitor is inputted to a comparator circuit having the hysteresis characteristic for comparison with the reference voltage. Accordingly, a switch may be controlled for ON and OFF states.