Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7091757
    Abstract: The object of the invention is to provide a frequency generator which is composed of an oscillator and a frequency doubler and in which difference in amplitude between differential outputs of the frequency doubler can be equalized at low power consumption without adjustment. To achieve the object, the amplitude of differential outputs of the frequency doubler is detected and the delay time of a variable delay circuit is controlled. Owing to this configuration, in case a frequency of the oscillator varies or in case delay time by the delay circuit used in the frequency doubler varies by process variation and others even if the frequency is fixed, the amplitude of the differential outputs of the frequency doubler can be also equalized in the frequency generator.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: August 15, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Toru Masuda
  • Patent number: 7091634
    Abstract: Disclosed is eyewear that may have a half-jacket frame and a removable dust shield for preventing direct impingement of dust upon a wearer's eye. The eyewear may have a titanium frame and removable lenses free of any attachment structure. The frame may have a lens-retaining ridge with a thin cross section. A nosepad on the frame may carry a shield retainer for releasably affixing a shield to the frame. The nosepad and the half-jacket frame front may be cast together in one piece out of titanium or titanium alloy. An anti-slip nosepad cover may partially cover the nosepad and leave the shield retainer exposed. A removable shield may have a lower lens groove that circumferentially mates with an upper lens groove of an orbital of a half-jacket frame, thereby circumferentially completing the lens groove when the shield is in place. A rigid temple may carry a slip resistor for contacting the wearer's skin. The eyewear may have a vent to reduce fogging of the lenses and the shield may be air-permeable.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: August 15, 2006
    Assignee: KBC America, Inc.
    Inventors: Kenyon Yi, Kyung Min
  • Patent number: 7086630
    Abstract: A fastener 1 in which a base 6, pipe holders 7a–7d, a stud engaging portion 10 for engaging a stud on a support, and an anchor engaging portion 9 for engaging a mounting hole in a support are molded integrally, whereby slender objects such as pipes held by the pipe holders are fastened to a support. The anchor engaging portion 9 is molded in an anchor shape and comprises a rigid shank 15 extending downwards perpendicularly from the base 6. A pair of flexible legs 17 extend from the end of the shank towards the base and bend away from the shank for engaging an edge of a mounting hole in a support. The fastener can be manufactured by a simple die structure without a slide.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: August 8, 2006
    Assignee: Newfrey LLC
    Inventor: Toshio Maruyama
  • Patent number: 7088519
    Abstract: The object is to provide a zoom lens system having a zoom ratio of 2.5 or more, compactness and high optical performance, applicable to a plurality of imaging devices with different image heights. According to one aspect of the present invention, a zoom lens system applicable to a plurality of imaging devices having different image heights with each other by partially sharing zooming trajectories without changing an optical element of the zoom lens system.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 8, 2006
    Assignee: Nikon Corporation
    Inventor: Daisaku Arai
  • Patent number: 7085157
    Abstract: A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: August 1, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiro Tanaka, Takashi Yamaki, Yutaka Shinagawa, Daisuke Okada, Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru
  • Patent number: 7082663
    Abstract: A method and apparatus in which a workpiece is supported on one arm of a C-shaped counterforce structure and is operated upon by a mechanism supported on the other arm of the counterforce structure. The operation causes deformation of the counterforce structure, which is measured, and the operation is adjusted responsive to the measured deformation.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: August 1, 2006
    Assignee: Newfrey LLC
    Inventors: Michael Blöcher, Joachim Möser, Reinhold Opper
  • Patent number: 7077151
    Abstract: A product fill system and method uses a mode valve. The mode valve is a shuttle valve that allows the shock tube to communicate with the filler valve during a fill operation corresponding to fill mode of the mode valve. If the filler valve is shut off, any overpressure can pass through the mode valve and be absorbed by the shock tube. The mode valve can be switched into a clean mode in which the shock tube is connected more directly in the circuit between the upstream side of the mode valve and the filler valve. In other words, the shock tube is on a side circuit of the main circuit used for product feeding during the fill operation. However, during the clean operation, the shock tube is in the circuit such that cleaning material travels completely throughout the shock tube. The method of the present invention involves the use of the product fill system so as to accommodate cleaning without disassembly of parts.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: July 18, 2006
    Inventors: Tomasz R. Targosz, Randy Steffen
  • Patent number: 7080331
    Abstract: The invention relates to a method for automatic recognition of simulation configurations of integrated circuits under design comprising at least two components connected to one another directly or indirectly, for the functional verification of the integrated circuits through simulation tests. The method includes a step for the acquisition of a simulation configuration by a server manager, a step for the sending of a request by a client manager to the server manager, a step for sending a response by the server manager to the client manager, and a step for the comparison by the client manager of the response with the requirements of the test, followed by a step for the disabling, activation and/or modification of certain parts of the test by the client manager in order to adapt the test to the configuration or signaling an error if the test cannot be adapted to the configuration.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: July 18, 2006
    Assignee: Bull, S.A.
    Inventor: Andrzej Wozniak
  • Patent number: 7078975
    Abstract: The present invention provides a power amplifier module featuring that: its output power characteristic smoothly changes as the input control voltage changes; and its control sensitivity is stable over a wide dynamic range. By same means, idling current for gain setting is supplied to a single amplifier element or all of multiple stages of amplifier elements of the power amplifier module. By making this idling current behave so as to exponentially change, relative to input control voltage, the invention enables output power control proportional to the input control voltage.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: July 18, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kiichi Yamashita, Tomonori Tanoue, Shizuo Kondo
  • Patent number: 7075469
    Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: July 11, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yada, Yasuyuki Saito
  • Patent number: 7073637
    Abstract: A double-wrap band brake apparatus has a double-wrap brake band comprising an annular intermediate band a pair of annular outer bands. The brake apparatus is used to brake a rotating member fitted in the double-wrap brake band. A center deviation correcting member is provided for correcting a center deviation between the intermediate band and the outer bands.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: July 11, 2006
    Assignee: NSK-Warner K.K.
    Inventors: Toshiaki Wakisaka, Masaki Sakai
  • Patent number: 7076601
    Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: July 11, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Miura, Kazushige Ayukawa
  • Patent number: 7073699
    Abstract: A fastening tool applies parts, in particular plastic parts, to objects. The plastic parts are supplied in the form of a belt in which the plastic parts are linked together by at least one flexible web. The fastening tool transports the belt by a feed mechanism such that one plastic part at a time is delivered to a fastening position. The feed mechanism has a fluid drive that is coupled by a translation-rotation converter to a transport gear rotatably mounted on the fastening tool and designed to positively or nonpositively engage the belt in order to transport it. The translation-rotation converter has an overrunning clutch whose driving gear is kinematically coupled to the fluid drive and whose driven gear is coupled to the transport gear in a rotationally fixed manner.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 11, 2006
    Assignee: Newfrey LLC
    Inventor: Dieter Seidler
  • Patent number: 7075734
    Abstract: A zoom lens system having an exit pupil far away from the image plane, zoom ratio of about three, and in particular having compactness and high optical performance includes, in order from an object, a first lens group having negative refractive power, an aperture stop, a second lens group having positive refractive power, and a third lens group having positive refractive power. When zooming from a wide-angle end state to a telephoto end state, the first and second lens groups are moved and the third lens group is fixed such that a distance between the first lens group and the second lens group varies, and a distance between the second lens group and the third lens group increases. The second lens group is composed of four lenses or less and includes a diffractive optical surface formed on a lens surface except the most object side lens surface.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: July 11, 2006
    Assignee: Nikon Corporation
    Inventor: Kenzaburo Suzuki
  • Patent number: 7076317
    Abstract: A flagship line 1 includes a job shop environment and a flow shop environment where three different standalone processing apparatuses for different steps constitute the job shop environment and two different serial processing apparatuses constitute the flow shop environment. One of the two serial processing apparatuses as a first serial processing apparatus 8 consists of a die bonder 5, a clean cure unit 6, and a wire bonder 7 and sequentially performs die bonding, clean cure and wire bonding. The other or second serial processing apparatus 13 consists of a marking unit 9, a cutting unit 10, a testing unit 11, and a visual inspection unit 12 and sequentially performs marking, lead cutting, testing, and visual inspection. The three standalone processing apparatuses are a dicing apparatus 2, a molding apparatus 4, and a visual inspection apparatus 3. This not only minimizes the possibility of a stagnant flow of workpieces between steps but also substantially shortens the overall processing time.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: July 11, 2006
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Yuuki Yamate, Shuuetsu Yoshino, Toshimichi Suzuki, Naohiro Hirai
  • Patent number: 7073997
    Abstract: An assembly includes a piece to be held in a bore and a device in which the piece is inserted for holding the piece in the bore. The device comprises a cylindrical sleeve having a series of fins extending longitudinally of an inner surface of the sleeve and projecting inwardly from the inner surface. The fins are skewed in a same circumferential direction relative to radial planes of the sleeve. The sleeve and the fins are integrally formed of resilient flexible plastic. The flexibility of the fins is such that the fins can be readily deflected when engaged by an inserted piece. The device can be used as part of a combination that includes a body having a bore therein, and can be used in a method of holding a piece in a bore of a body.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: July 11, 2006
    Assignee: Newfrey LLC
    Inventor: Zdravko Kovac
  • Patent number: 7075825
    Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of rows and columns disposed substantially in a rectangle, with a plurality of word lines coupled with memory gate electrodes intersecting a first side of the rectangle substantially perpendicularly, a plurality of bit lines coupled with memory drain-source current paths intersecting a second side of the rectangle substantially perpendicularly (the second side also substantially perpendicularly intersecting the first side), a row select circuit being disposed at the first side for coupling with the word lines, and peripheral circuitry including a column select circuit and a sense circuit being disposed at the second side.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: July 11, 2006
    Assignee: BTG International Inc.
    Inventor: Gerald J. Banks
  • Patent number: 7069809
    Abstract: A tilt adjustable type steering apparatus for a vehicle is constructed such that a rear column member is connected in a swayable manner within an on-driving tilt adjustable range to a front column member fixed to a car body, a fixed gear provided on one of the front column member and the rear column member is engaged with a movable gear provided on the other of the front column member and the rear column member when fixing the rear column member to a tilt adjusted position, and the two fixed and movable gears are disengaged from each other by swaying the movable gear when releasing the rear column member from the tilt adjusted position. The same apparatus includes a spring and/or a lock mechanism, which enables the rear column member to be tilted up to an upper predetermined position in excess of the on-driving tilt adjustable range and holds in this position the rear column member tilted up to the predetermined position.
    Type: Grant
    Filed: December 25, 2002
    Date of Patent: July 4, 2006
    Assignee: NSK, Ltd.
    Inventors: Kenji Sato, Yasuhiro Shibuya
  • Patent number: 7072242
    Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: July 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
  • Patent number: 7070113
    Abstract: A nonvolatile memory has an erase table in which a free-space information flag is associated with each physical address of a memory area and an address translation table in which a physical address of a memory area is associated with each logical address. The free-space information flag indicates whether a corresponding memory area is permitted to be erased. A control circuit determines a memory area to which rewrite data is to be written by referring to the free-space information flag, reflects the physical address and the logical address of the memory area to which the data is written into the address translation table, and updates the free-space information flag. The memory area to which rewrite data is to be written is determined by referring to the free-space information flag, and rewriting is not performed in the same memory area.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 4, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Atsushi Shiraishi, Takayuki Tamura, Chiaki Kumahara, Shinsuke Asari