Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.

Abstract: In a method of forming a pattern and a method of forming a capacitor, an oxide layer pattern having an opening is formed on a substrate. A conductive layer is formed on the oxide layer pattern and the bottom and sidewalls of the opening. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern including a siloxane polymer. The conductive layer on the oxide layer pattern is selectively removed using the buffer layer pattern as an etching mask. A conductive pattern having a cylindrical shape can be formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

Abstract: A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.

Abstract: A voltage-controlled oscillator (VCO) circuit includes a level shifter, and a semiconductor device includes the VCO circuit. The VCO circuit includes an input voltage receiver, a current mirror, and a frequency oscillator. The input voltage receiver receives a first voltage input to the VCO circuit so as to generate a first current. The current mirror copies the first current so as to generate a second current. The frequency oscillator oscillates in response to the second current. The input voltage receiver includes a level shifter and a first current generator. The level shifter shifts a voltage level of the first voltage to a voltage level of a second voltage. The first current generator generates the first current corresponding to the second voltage.

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.

Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.

Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.

Abstract: Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.

Abstract: A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

Abstract: An innovative oil observer for estimating oil concentration and oil amount in a refrigerant compressor in a vapor compression cycle is described. The invention ensures the safe operation of the compressor by ensuring that adequate lubricant is present in the compressor. This oil observer is based on oil models for components of air conditioning and refrigeration systems. Oil models for HVAC components estimate oil mass and refrigerant mass in each component. With all component oil models and heat exchanger observers which provide the estimation of inner geometric lengths of two-phase flow heat exchangers, a system-level oil observer is established by integrating all component models. Experimental testing has been conducted to verify the performance of this oil observer for steady state operation and dynamic processes. The invention has direct applications in residential and commercial air conditioning and refrigeration systems.

Abstract: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Abstract: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

Abstract: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.

Abstract: A test system includes: a tester; and a test board, on which a multi-chip package including plural memories is mounted, being connected to the tester by way of a transmission line. The transmission line includes a compensation unit for compensating signal distortion.

Abstract: In an embodiment, an LVDS (Low Voltage Differential Signaling) receiver includes at least one LVDS input buffer, a clock generating unit, and a bias circuit. The clock generating unit includes a voltage controlled oscillator for generating a clock signal tracking a frequency of data received via the at least one LVDS input buffer based on a control voltage. The bias circuit controls current sources that supply current to at least one differential amplifier in the at least one LVDS input buffer based on the control voltage of the clock signal generating unit. Therefore, the LVDS receiver can save current consumed in LVDS input buffers by controlling the amount of current supplied to the at least one differential amplifier included in the at least one LVDS input buffers.

Abstract: A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by measuring electrical characteristics of the plurality of transistors included in the plurality of chips, extracting an inter-chip distribution characteristic and an intra-chip distribution characteristic of the electrical characteristics by analyzing the electrical characteristic data, generating random number data satisfying the extracted inter-chip and intra-chip distribution characteristics, and performing a simulation for extracting statistical distribution characteristic data of the physical parameters of the chips, based on the random number data.

Abstract: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device.