Abstract: In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.

Abstract: In an embodiment, a semiconductor device is tested using a probe pad that includes a probing region with which a probe needle makes contact, and a sensing region bordering an edge of the probing region. Electrical signals are applied, and measured results indicate the probe needle's location relative to a test position on the semiconductor device.

Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Abstract: A low-profile signal device is provided having a plurality of light emitters disposed on at least one support member, the plurality of light emitters configured to emit light in a plurality of colors that indicate one or more predefined conditions; a housing substantially enclosing the at least one support member; a signal interface coupled to the plurality of light emitters and configured to selectively activate light emitters from the plurality of light emitters in response to a received control signal.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.

Abstract: A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device.

Abstract: Provided are a semiconductor package in which bonding pads of a semiconductor chip are electrically connected to interconnection portions by wire-bonding, and a method of manufacturing the semiconductor package. The semiconductor package includes: a substrate; an interconnection portion that is disposed on the substrate and comprises conductive patterns having a first thickness and conductive patterns having a second thickness that is smaller than the first thickness; at least one semiconductor chip that is mounted on the substrate and comprises a plurality of bonding pads; and a plurality of wires electrically connecting the conductive patterns and the bonding pads.

Abstract: A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

Abstract: An oscillator includes a first comparator circuit, a second comparator circuit, an oscillation signal generator circuit, and a frequency voltage generator circuit. The first comparator circuit generates a first pulse when a frequency voltage reaches a first reference voltage, and the second comparator circuit generates a second pulse when the frequency voltage reaches a second reference voltage. The oscillation signal generator circuit generates an oscillation signal by latching a first voltage in response to the first pulse and latching a second voltage in response to the second pulse. The frequency voltage generator circuit raises or lowers the frequency voltage in response to the oscillation signal. The driving capability of the first comparator circuit is reduced at the latching of the first voltage and is restored at the latching of the second voltage.

Abstract: Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.

Abstract: A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.

Abstract: A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

Abstract: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Abstract: In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.

Abstract: A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.

Abstract: New types of photocatalyst materials are disclosed together with methods for preparing and using these materials, as well as air treatment systems incorporating such materials. The photocatalyst materials of this invention consist essentially of very small particles of a first-metal oxide, the first-metal being a metal that exhibits photo-induced semiconductor properties, having ions of a second-metal dispersed throughout its lattice structure, the second-metal being selected from the group of dopant metals. Such photocatalyst materials are prepared by the steps of mixing first-metal and second-metal precursors, removing nonessential ions from the mixture, drying the resulting product, and calcinating the dried product to produce the completed photocatalyst material.

Abstract: In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A photoresist pattern is formed on the second insulation interlayer. The photoresist pattern has an exposed portion. The dummy pattern under the photoresist pattern is arranged to cross over the exposed portion of the photoresist pattern. The first and second insulation interlayers are etched using the photoresist pattern and the dummy pattern as an etching mask, to form a plurality of contact holes on both sides of the dummy pattern. Accordingly, the contact holes may be formed to have a smaller width.

Abstract: A fiber holder platform includes a support, a clamp configured to secure a cable to the support, and a securing mechanism configured to detachably secure the platform to a fiber holder and alternatively to a heat oven. A fiber holder assembly includes the fiber holder platform and the fiber holder, in a detachable or integral configuration.

Abstract: An amplifier for improving an electrostatic discharge (ESD) characteristic includes an operational amplifier, a first resistor circuit, a first fuse box, a second resistor circuit, and a second fuse box. The operational amplifier includes a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, and an output terminal outputting an output signal. The first resistor circuit is connected between the second input terminal and a first node to prevent ESD from being input to the second input terminal. The first fuse box is connected between the first node and the output terminal of the operational amplifier. The second resistor circuit is connected between the second input terminal and a second node to prevent ESD from being input to the second input terminal. The second fuse box is connected between the second node and a terminal for receiving a ground voltage.