Abstract: A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.

Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell transistor gates of first and second memory cell transistors on the substrate at opposite sides of the select transistor, each of the first and second memory cell transistor gates comprising: a tunnel insulating layer pattern; a charge storage layer pattern on the tunnel insulating layer pattern; a blocking insulating layer pattern on the charge storage layer pattern; and a control gate on the blocking insulating layer pattern; first and second floating junction regions in the substrate between the select transistor gate and the first and second memory cell transistor gates respectively; and first and second drain regions in the substrate at sides of the first and second memory cell transistor gates respectively opposite the first and second float

Abstract: Theft, distribution, and piracy of digital content on optical media (software, video, audio, e-books, any content of any kind that is digitally stored and distributed) is often accomplished by copying it directly to another disc using commonly available copy tools and recordable optical media, or the copying of media to another mass manufactured disc. Methods which cause the copy process to become lengthy and inconvenient, or which produce copies that are significantly measurably different from the original and therefore be recognizable as copies, may deter or prevent an unauthorized individual from making copies. In addition, methods which generate an intended slow-down in the read process of the media can be used to authenticate the media at run time. This offers significant advantages to content creators who wish to protect their products.

Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Abstract: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed.

Abstract: A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

Abstract: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.

Abstract: A phase locked loop includes a phase-frequency detector and a loop filter. The phase-frequency detector compares phases of an input signal and a feedback signal to generate first and second control signals. The loop filter includes a pull-up resistor, a pull-down resistor and a capacitance unit. The loop filter receives a first reference voltage to charge the capacitance unit through a path formed by the pull-up resistor to the capacitance unit, receives a second reference voltage to discharge the capacitance unit through a path formed by the pull-down resistor to the capacitance unit and outputs a control voltage generated based on a charge amount of the charged capacitance unit. Therefore, the phase locked loop can operate at a relatively low voltage and can operate based on a control voltage with a wide input range.

Abstract: In a semiconductor device having a plurality of fuses and a method of fabricating the same, the semiconductor device comprises an inter-layer dielectric layer on a semiconductor substrate; a plurality of fuses on the inter-layer dielectric layer, an inter-metallic dielectric layer on the plurality of fuses and the inter-layer dielectric layer, a passivation layer on the inter-metallic dielectric layer, fuse windows exposing portions of a top surface and sidewall surfaces of the plurality of fuses, and a fuse barrier pattern between adjacent ones of the plurality of the fuses.

Abstract: An integrated circuit apparatus including an improved test circuit and a method of testing the integrated circuit apparatus are provided. The integrated circuit apparatus determines pass or fail of the integrated circuit apparatus itself by comparing internal DQ data output by a core logic circuit with test patterns set by a mode register set (MRS) code or test patterns directly input from an external source.

Abstract: Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other can be increased, while an area of a junction region where the channel body contact source and drain regions can be reduced. As a result, capacitance of the channel body can be increased, and a generation of leakage current through the second junction region can be reduced. The application of a back bias to the cylindrical auxiliary gates can improve a charge storage capability of the channel body.

Abstract: In a display state control apparatus for automatically changing the frequency and the phase of a sampling clock signal according to changes in the phase and frequency of an input signal, and in a display state control method therefor, an optimal display state is maintained by automatically changing the frequency and phase of a sampling clock signal used to sample an input signal according to changes in the input signal. In this manner, user interaction is not required for generating the optimal display control signal.

Abstract: A multichip and method of testing a multichip, the multichip including a control chip having a central processing unit (CPU) and a plurality of memories, each memory of the plurality of memories storing information related to testing the multichip, comprises connecting one of the memories to the control chip; reading, by the CPU, stored memory information from the connected one of the memories to confirm the connected one of the memories; generating a test pattern relating to the connected one of the memories confirmed by the CPU, and testing the connected one of the memories according to the test pattern.

Abstract: A photomask according to the invention provides selective regional optimization of illumination type according to the type of image being formed using the photomask. The photomask include a light polarizing structure which polarizes the light incident on the polarizing structure. Light of a first illumination type from a source in a photolithographic exposure system is incident on the photomask. A portion of the light is incident on the region of the photomask that includes the polarizing structure, and another portion of the light is incident on another region of the photomask that does not include a polarizing structure. The illumination type of the light incident on the polarizing structure is changed to a second illumination type such that light incident on a substrate such as an integrated circuit wafer from the region of the photomask that has the polarizing structure is of the second illumination type.

Abstract: In an image processing apparatus and method, image data includes both color and alpha components. During processing, only the color component of the image data is stored in a memory. Display image data are then generated in response to the color component data retrieved from the memory and the alpha component data that were not stored in the memory. In this manner, by not storing the alpha component data in the memory, the memory access load by the image processing system is reduced.

Abstract: A self-closing cable feed-through module is connected to an outer surface of the chamber. The feed-through module includes a first portion and a second portion, wherein cables are fed through the first and second portions into the chamber in a first position and the first and second portions form a leak tight seal around the cables in a second position.