Abstract: A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

Abstract: In an image sensor and a method for forming the same, the method comprises: preparing a substrate having a pixel array region and a peripheral circuit region; sequentially stacking a gate electrode layer and a mask layer on the substrate; patterning the gate electrode layer and the mask layer to form a gate pattern; implanting impurities in the substrate in the pixel array region to form a photoelectric conversion region; and removing the mask layer.

Abstract: In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.

Abstract: In an image sensor in which a vertical length from a photoelectric conversion element to an uppermost micro-lens is minimal, and a method of manufacturing the same, the image sensor includes a substrate, a plurality of photoelectric conversion elements, and first to n-level (where n is an integer greater than or equal to 2) metal wires. In the substrate, a sensor region and a peripheral circuit region are defined. The plurality of photoelectric conversion elements are formed in or on the substrate within the sensor region. The first to n-level metal wires are sequentially formed on the substrate. The n-level metal wires within the sensor region are of a thickness that is less than the n-level metal wires within the peripheral circuit region.

Abstract: A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench.

Abstract: Provided are a doping mask and methods of manufacturing a charge transfer image device and a microelectronic device using the same. The method includes forming a photoresist film on an entire surface of a substrate or sub-substrate having a peripheral circuit region and a pixel region, removing the photoresist film on an upper surface of the substrate intended for the peripheral circuit region and patterning the photoresist film on an upper surface of the substrate intended for the pixel region to form a photoresist pattern having an array of openings with a predetermined pitch, implanting ions at the same concentration level into the entire surface of the substrate using the photoresist pattern as a doping mask, and diffusing the implanted ions by annealing. The pitch is determined so that ions implanted through each opening diffuse toward those implanted through an adjacent one to form wells.

Abstract: In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern.

Abstract: A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power or ground voltage; and an output unit that inverts a logic level of the fighting node to generate the gated clock signal. A blocking unit can be included that blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. A blocking transistor can be included that prevents unnecessary electric charge from inflowing into the fighting node to reduce power consumption and discharging time.

Abstract: A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.

Abstract: A recording apparatus for generating write pulse control signals suitable for various optical recording media includes a pattern detector receiving a non return to zero inverted (NRZI) signal and distinguishing between information about a mark and information about a space, a memory storing timing parameters for a start pulse, a middle pulse, an ending pulse, and a cooling pulse of the write pulses corresponding to each of the various recording media using an activation table or in an index remapping method, a parameter fetcher fetching suitable timing parameters from the memory in response to a result of the distinguishing by the pattern detector, and a write pulse generator generating the write pulses based on the timing parameters received from the parameter fetcher and information stored in a register.

Abstract: In a method of interfacing a high-speed signal, a series of digital signals are received from a transmitter in response to a clock signal. The received digital signal is coded based on a K-L level pulse amplitude modulation system in response to the clock signal, wherein K and L are natural numbers and K?L. The received digital signal is repeatedly coded and the coded digital signal is transferred to a receiver. As a result, crosstalk between adjacent channels may be reduced.

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.

Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.

Abstract: A non-volatile memory device having an asymmetric channel structure is provided.

Abstract: A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.

Abstract: A pre-emphasis apparatus of a LVDS transmitter includes a pre-emphasis signaling generation unit and a pre-emphasis current output unit. The pre-emphasis signal generation unit generates a pre-emphasis pulse signal based on N parallel data signals received from an external source and N-phase clock signals received from a phase locked loop, where N is an integer greater than 1. The pre-emphasis current output unit provides an additional current for a pre-emphasis operation to a current source of a LVDS driver in response to the pre-emphasis pulse signal generated by the pre-emphasis pulse signal generation unit. The pulse signal for pre-emphasis is generated based on the parallel data signals received from the external source and the multi-phase clock signals, which are output from the phase locked loop for performing a sampling of the parallel data signals.

Abstract: Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions.

Abstract: Provided are magnetic tunnel junction structures having bended tips at both ends thereof, magnetic RAM cells employing the same and photo masks used in formation thereof. The magnetic tunnel junction structures have a pinned layer pattern, a tunneling insulation layer pattern and a free layer pattern, which are stacked on an integrated circuit substrate. At least the free layer pattern has a main body as well as first and second bended tips each protruded from both ends of the main body when viewed from a plan view.

Abstract: There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

Abstract: A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.