Abstract: A data qualification circuit (11) comprises a comparator (28), a first threshold circuit (33), and a second threshold circuit (41). A differential input signal is applied to the data qualification circuit (11). A first threshold circuit (33) is enabled by a zero logic state at the output of comparator (28). The first threshold circuit (33) sets a one logic state threshold voltage which the differential input signal must overcome for the comparator (28) to generate a one logic state. A second threshold circuit (41) is enabled by a zero logic state at the output of comparator (28). The second threshold circuit (41) sets a zero logic state threshold voltage which the differential input signal must overcome for the comparator (28) to generate a zero logic state.

Abstract: An etch stop layer prevents damage to the underlying semiconductor material or metallization layer during etching of a dielectric layer overlying the etch stop layer. The etch stop layer, aluminum nitride or aluminum oxide is used underlying silicon dioxide to prevent damage to the semiconductor material during a fluorocarbon based etch of the silicon dioxide. The etch stop layer is also used underlying a silicon dioxide layer and overlying a titanium nitride or titanium tungsten layer used in metallization to prevent etching of the titanium nitride or titanium tungsten layer during etching of the silicon dioxide.

Abstract: A method of removing dam bars (15) from leads (17) of a semiconductor chip package (10) is performed by first breaking a bond between the dam bars (15) and excess mold compound (12) from a mold compound (11). The bond is broken by slight movement of the dam bar (15). Thereafter, the dam bar (15) is completely removed by moving the dam bar (15) further, without causing chips or cracks in the mold compound (11).

Abstract: An apparatus for and method of decomposing a chemical compound, which may be an environmentally undesirable material, is accomplished by impinging a flow of the chemical compound on a heated member. Various embodiments are possible, including having the member have a plurality of openings, having the member be configured to direct the flow of the chemical compound in a particular direction, and having the member be self supported on the wall of the reaction chamber.

Abstract: An insulated gate semiconductor device (10) is fabricated by providing at least one ballast resistor (40) having a sheet resistance of at least one square. The ballast resistor (40) is formed in the emitter region (17) between two adjacent portions of the base region (26) at the top surface of the semiconductor body in which the device (10) is fabricated. The ballast resistor (40) improves the latch resistance of the device (10) in overload conditions.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Abstract: A method and apparatus for plating metals which delivers a voltage pulse with the possibility of a widely varying current magnitude characteristic to a plating electrode and an object having a large electrical reactance in terms of a parallel resistance and capacitance in order to raise the voltage potential between the electrode and an object to a programmed plating voltage overpotential and underpotential. The programmed plating voltage overpotential determines how fast the electrochemical reaction is allowed to proceed in the diffusion layer, and the programmed voltage underpotential determines how quickly the electrochemical reaction of the diffusion layer will slow down.

Abstract: An edge die bond semiconductor package including a semiconductor die having an active major surface and a mounting edge substantially orthogonal to the active surface, a base having a mounting surface, and material affixing the mounting edge of the semiconductor die to the mounting surface of the base.

Abstract: Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Abstract: A micromachined structure having at least one anchor that includes a supporting substrate with a first and a second foot fixedly positioned on the surface of the substrate and each foot has a supporting edge, which edges are positioned in parallel spaced apart relationship, an elongated tether positioned in spaced relation from the surface of the substrate and extending from the micromachined structure parallel to the parallel supporting edges of the first and the second foot, and first and second risers extending along the supporting edges of the first foot and the second foot, respectively, and rising upwardly to the edges of the tether. The first and the second foot, the first and second risers and the tether being formed integrally by surface micromachining.

Abstract: A method for forming conductive interconnect bumps, such as solder bumps, on bond pads on a substrate. The method includes conductive discs and a connecting member formed between two adjacent conductive discs. The discs and connecting member are then placed over the bond pads and heat is applied so that the conductive discs and the connecting member combine to form isolated interconnect bumps. A polymer backsheet is used for support.

Abstract: A large sense voltage is produced by the semiconductor device of the present invention. The semiconductor device, utilizing current mirror techniques, is comprised of a power MOSFET having a plurality of power cells and a plurality of sense cells formed in a semiconductor epitaxial layer. The large sense voltage is provided by isolating and separating the plurality of power cells from the plurality of sense cells by at least the thickness of the semiconductor epitaxial layer. Isolation can be provided by forming a plurality of inactive cells or an elongated cell between the plurality of power cells and the plurality of sense cells. In addition, high voltage capabilities can be maintained by including a partially active region adjacent the power cells to provide for good termination.

Abstract: A method of fabricating a fast-switching, low-R(on) insulated-gate bipolar transistor including providing an N-type semiconductor wafer with a planar surface, forming a thin heavily-doped layer, having a concentration in the range of 3.times.10.sup.17 /cm.sup.3 to 1.times.10.sup.19 /cm.sup.3, in the wafer adjacent the planar surface, providing a P-type semiconductor wafer, and bonding a surface of the P-type wafer to the planar surface of the N-type wafer. An emitter and a gate are then formed in the N-type wafer in the usual manner and a collector is formed on the P-type wafer.

Abstract: A leadframe (10) formed by a method including providing a preform of silicon carbide, placing the preform in a mold, injecting a liquefied metal, such as aluminum, into the mold to fill the mold and infiltrate the preform, using heat and pressure. The mold defines a mounting area (12) in which the preform is positioned, and a plurality of leads (20, 22, 28, 29).

Abstract: A connector affixed to the end of a cable of optical fibers and having alignment pins extending axially in parallel with the cable and beyond the end thereof. A substrate with alignment holes and light transmitting openings therethrough in axial alignment with the ends of the optical fibers when the alignment pins and holes are engaged. The substrate including mounting pads, electrical connection pins and electrical traces connecting the pads to the pins. A semiconductor die, with photonic devices thereon, mounted on the mounting pads of the substrate so that each photonic device is aligned with a light transmitting opening and electrically connected to the electrical connection pins. A sleeve surrounding and securing the connector to the mounting member.

Abstract: A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Abstract: A method of fabricating a MESFET is comprised of providing a semiconductor material having a channel region formed therein, forming a gate on the semiconductor material over the channel region, forming a spacer adjacent a first portion of the gate disposed on the semiconductor material, and forming a hard mask disposed on a second portion of the gate and on a portion of the semiconductor material.

Abstract: A semiconductor chip package is manufactured comprising a heatsink bonded to an aluminum nitride insulative layer by a thermally conductive and electrically nonconductive epoxy. The aluminum nitride insulative layer is bonded to several portions of a leadframe by an epoxy which is thermally conductive and electrically nonconductive and another epoxy which is thermally conductive and electrically conductive. A semiconductor die is bonded to the aluminum nitride insulative layer by a thermally conductive and electrically conductive epoxy.

Abstract: A semiconductor device is fabricated which has reduced power dissipation when the device is turned on and runs cooler in surge suppressor applications. This result is achieved by fabricating a device where the breakdown action takes place preferentially under cathode region. The lower power dissipated during the turn-on action enables the device to operate in environmental conditions from -20.degree. C. to 65.degree. C.