Abstract: A superluminescent edge emitting device is fabricated to have apparent vertical light emission. The superluminescent device is comprised of a semiconductor supporting structure having a major surface. A light emitting portion is formed above a first portion of the major surface, wherein the light emitting portion is configured in a substantially circular shape to suppress lasing and has sidewalls, and wherein light is emitted from the sidewalls of the light emitting portion. An non-emitting portion is formed above a second portion of the major surface and adjacent to the light emitting portion, wherein the non-emitting portion has sidewalls, and wherein the sidewalls of the light emitting portion and the sidewalls of the non-emitting portion are configured to direct the light emitted from the light emitting portion substantially perpendicular to the major surface.

Abstract: A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.

Abstract: A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Abstract: A layer is plasma etched or deposited with a gaseous mixture of a hydrocarbon, hydrogen and a noble gas. A cathode DC bias of greater than 600 V is used. This cathode DC bias allows for selectively etching a III-V material over an aluminum containing layer or for the deposition of a hydrogenated carbon film.

Abstract: A semiconductor chip module is formed by providing at least one semiconductor chip and a semiconductor substrate and bonding the semiconductor chip to the semiconductor substrate without the use of an epoxy or a metallic layer to create a bond between the semiconductor chip and the semiconductor substrate. The semiconductor chip of the semiconductor chip module is electrically connected to an external, electrical interconnection system. The semiconductor substrate has similar thermal properties to the semiconductor chip, this thermal mismatch present between a semiconductor chip and a metallic heatsink in conventional external, electrical interconnection systems is eliminated.

Abstract: An interconnect for coupling optical fibers and photonic devices. This interconnect is comprised of a fiber bundle formed of a plurality of optical fibers, a plurality of photonic devices, and a connector assembly. The connector assembly is comprised of a first connector and a second connector. The first connector is coupled to the fiber bundle and the second connector is coupled to the plurality of photonic devices. When the first connector and second connector are coupled together in a single connection, the photonic devices align with the optical fibers for optical communication.

Abstract: A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

Abstract: A method for cleaning a processing tube is performed by an apparatus providing a vacuum and a flow of an inert gas. The flow of the inert gas dislodges particles from the tube surface and assists in carrying the particles to the vacuum. The vacuum is centered in the tube, thus preventing the sides of the tube from being scraped. Wheels are attached to the vacuum means to facilitate cleaning of the tube.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: A semiconductor chip is flip chip bonded to a substrate having a cavity or a through hole formed therein. The cavity or through hole is preferably large enough to substantially remove the narrow gap which is formed between the portion of the substrate which does not have the cavity or through hole formed therein. This allows for use of mold processes to encapsulate and underfill the semiconductor chip and for line of sight cleaning of the semiconductor chip after bonding.

Abstract: A semiconductor device having a short gate length is fabricated. The short gate length is obtained by utilizing the fact that an unannealed silicon nitride can be isotropically etched while not etching an annealed silicon nitride layer. The method comprises forming a first silicon nitride 13 on a semiconductor material 10, annealing layer 13, forming an insulating layer 15, a second silicon nitride layer 17 and a masking layer 19, undercutting a portion of layers 17 and 15, removing the masking layer, annealing the second silicon nitride 17, implanting to form channel region 20 having portions 21 and 22, undercutting a portion of the insulating layer 15, removing the second silicon nitride 17 and the first silicon nitride 13 not covered by layer 15, forming gate 23 having effective gate length 30 and source/drain 25/26.

Abstract: A process for forming a lateral bipolar transistor wherein apertures for forming a current electrode (collector or emitter) region, a base region and an isolation region are all formed simultaneously so that they are automatically aligned. Also, a mask area covering the base region when the current electrode region is being doped only covers the base (oversize) region. The mask is easier to remove after it has itself been doped/cured during the implantation process because it is smaller.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: A non-strained epitaxial layer is formed to have a small transition width and a low amount or no amount of oxygen incorporated therein. During the formation of non-strained epitaxial layer, a germanium source gas is introduced. Germanium reacts with water and/or oxygen to form GeO, which sublimates from the surface of the non-strained epitaxial layer, instead of oxygen being incorporated into the lattice. Thus, a low temperature epitaxial process can be used to obtain the small transition width without having oxygen incorporated into the non-strained epitaxial layer.

Abstract: An alignment signal is analyzed asymmetrically using any means of artificial intelligence or similar logic to apply empirical or theoretical offsets to signal position calculations based on the unique signal shapes of the different signals collected. A database of signal shapes and correlated offsets is used to improve subsequent alignment steps. For example, a case-based reasoning method can be used.

Abstract: A portion of a semiconductor die is rigidly flip chip bonded to a conductive base plate and portion is bonded to a flexible dielectric material to take advantage of the benefits of flip chip packaging while at the same time allowing for heat to be dissipated and for differential thermal expansion to be relieved. A semiconductor die having at least a first and a second bump formed thereon is rigidly connected to the base plate through the first bump and is flexibly connected to the base plate through the second bump.

Abstract: A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.

Abstract: A vertical cavity surface emitting laser (VCSEL) having sensing capabilities is fabricated by forming a layer having the capability to change the threshold current of the VCSEL. This can be accomplished by forming a deformable membrane or a cantilevered beam on the VCSEL. The deformation of movement of the beam causes a change in the threshold current of the VCSEL, so that it can go from lasing to nonlasing or vice versa. In addition, a layer which changes reflectivity in the presence of a particular chemical can also be formed on the VCSEL to produce the same result.

Abstract: New formulations for the electrodeposition of a dense, reflective tin or tin-lead alloy on a cathode have been developed. Such electrodeposition solutions are partially comprised of an additive which is comprised of at least one nonionic surfactant which is electrolyzed prior to starting the electrodeposition process. The electrodeposition solution is also comprised of an amount of an aliphatic dialdehyde kept low enough so that the solder deposits contain no more than 500 ppm of co-electrodeposited carbon. The additive and the aliphatic dialdehyde is mixed with a solution comprised of an alkane or alkanol sulfonic acid and a tin alkane or alkanol sulfonate or a mixture of a tin and lead alkane or alkanol sulfonate to form an electrodeposition solution. A dense, reflective finish is then electrodeposited on a cathode by using such an electrodeposition solution.